What value does SLTU write?
It writes 1 when the comparison is true, otherwise 0.
SLTU
RISC-V SLTU Instruction Details
Instruction ManualR-typeSet rd to 1 if rs1 is less than rs2 (unsigned), else 0
Instruction Syntax
sltu rd, rs1, rs2
Operand Breakdown
rd: selects x0–x31; overlap uses source values before writeback, and x0 writes are discarded.
rs1, rs2: XLEN-bit sources interpreted as unsigned integers.
rd is 1 if less, otherwise 0; this is not a conditional branch.
RV32IRV64IArithmeticCompare
Instruction Behavior
SLTU compares rs1 and rs2 as unsigned integers, setting rd to 1 if rs1 < rs2, else 0. funct7=0000000, funct3=011. SLTU rd,x0,rs2 sets rd=1 if rs2 != 0 (pseudo SNEZ).
SLTU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sltu
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
tp(x4)
0x00000004
s1(x9)
0x00000009
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
01001
rs2
00100
rs1
011
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x009232B3
opcode
0110011 -> OP
funct3
011 -> SLTU
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / tp(x4) / s1(x9)
ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x009232B3
syntax : sltu t0(x5), tp(x4), s1(x9)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLTU performs unsigned comparison rs1 < rs2; rd is set to 1 when true and 0 otherwise. It turns a comparison result into an integer value usable by later arithmetic or branches.
The register form compares rs1 with rs2.
Signed and unsigned comparisons differ in how the bit patterns are interpreted, not in register width.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «sltu x5, x6, x7 # x5 = (x6 < x7) ? 1 : 0 (unsigned)».
Pre-Use Checklist
Syntax Check
- Registers select x0–x31; overlapping operands read values before writeback.
- This R-type form has no immediate; SRA uses only the effective low rs2 bits.
Semantic Check
- Use the instruction's signed/unsigned comparison interpretation or arithmetic sign-fill rule.
- rd=x0 is a HINT with unchanged general registers; SRAI x0,x0,7 is the semihosting exit marker.
Pitfalls / Common Confusions
Use SLT for signed comparison
x0 as rs1 tests for rs2 != 0
With rd=x0, SLTU is a custom HINT: general registers remain unchanged and the PC advances normally.
FAQ
What is the difference between SLT and SLTU?
SLT/SLTI compare as signed integers; SLTU/SLTIU compare as unsigned integers.