What value does SLT write?
It writes 1 when the comparison is true, otherwise 0.
SLT
RISC-V SLT Instruction Details
Instruction ManualR-typeSet rd to 1 if rs1 is less than rs2 (signed), else 0
Instruction Syntax
slt rd, rs1, rs2
Operand Breakdown
rd: selects x0–x31; writes to x0 are discarded. rs1: supplies the source value before writeback.
rs2: supplies the second XLEN-bit source; both sources are compared as signed integers.
rd is 1 when the comparison is true, otherwise 0; control flow is unchanged.
RV32IRV64IArithmeticCompare
Instruction Behavior
SLT is an R-type instruction that compares rs1 and rs2 as signed integers, writing 1 to rd when rs1 < rs2 and 0 otherwise. opcode=0110011, funct7=0000000, funct3=010.
SLT Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
slt
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
a6(x16)
0xFFFFFFF0
sp(x2)
0x00000002
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00010
rs2
10000
rs1
010
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x002822B3
opcode
0110011 -> OP
funct3
010 -> SLT
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / a6(x16) / sp(x2)
ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x002822B3
syntax : slt t0(x5), a6(x16), sp(x2)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLT performs signed comparison rs1 < rs2; rd is set to 1 when true and 0 otherwise. It turns a comparison result into an integer value usable by later arithmetic or branches.
The register form compares rs1 with rs2.
Signed and unsigned comparisons differ in how the bit patterns are interpreted, not in register width.
Common Usage Scenarios
Signed comparison
RV32I/RV64I, x6=-16 and x7=2: slt x5, x6, x7 compares signed values and gives x5=1; equality gives zero.
Pre-Use Checklist
Syntax Check
- Register operands select x0–x31 or their ABI names; sources use values before writeback.
- rd, rs1 and rs2 are register fields with no immediate operand.
Semantic Check
- Set rd to 1 if rs1 is less than rs2 (signed), else 0
- x0 is always zero and discards writes; integer computation raises no arithmetic exception.
Pitfalls / Common Confusions
Result is boolean (0 or 1), not the difference value
Use SLTU for unsigned comparison
FAQ
What is the difference between SLT and SLTU?
SLT/SLTI compare as signed integers; SLTU/SLTIU compare as unsigned integers.