Add rs1 and rs2, place result in rd
ADD is an R-type instruction in the RISC-V RV32I/RV64I base integer set. Its assembly syntax is `add rd, rs1, rs2` — it adds the values in registers rs1 and rs2 and writes the result to rd. Overflow is silently ignored; only the lower XLEN bits are kept (32-bit result on RV32, 64-bit on RV64). ADD uses opcode 0110011 with funct3=000 and funct7=0000000. For immediate addition, use ADDI instead.
ADD uses R-type encoding (opcode=0110011, funct7=0000000, funct3=000). It adds integer registers rs1 and rs2, writes the low XLEN bits to rd, and raises no arithmetic-overflow exception. A write to rd=x0 is discarded; x0 remains zero.
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
ADD is register-to-register integer addition. In RV32I/RV64I semantics it adds rs1 and rs2, writes rd, does not trap on arithmetic overflow, and keeps the XLEN-wide result.
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Integer addition keeps only the low XLEN bits of the result; arithmetic overflow does not raise an exception. Software must add explicit checks when overflow detection is required.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, version 20260120, §2.4 Integer Computational InstructionsADD is an R-type instruction. Both operands come from rs1 and rs2, and the result is written to rd. Use ADDI for immediate addition.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, version 20260120, §2.4 Integer Computational InstructionsADD takes two register operands (rs1 + rs2), while ADDI takes one register and a 12-bit signed immediate (rs1 + imm). ADD is R-type (opcode 0110011); ADDI is I-type (opcode 0010011). ADDI's encodable immediate range is -2048 through 2047; ADD reads its second addend from rs2 rather than an immediate.
ADD and SUB are R-type instructions sharing opcode=0110011 and funct3=000. ADD has funct7=0000000 and computes rs1+rs2; SUB has funct7=0100000 and computes rs1-rs2. Both keep the low XLEN bits and raise no arithmetic-overflow exception.
Understand this scenario with real code like «add x5, x6, x7 # RV32I/RV64I: x6=20, x7=7 -> x5=27».
Understand this scenario with real code like «add x5, x6, x7 # RV32I/RV64I: x6=20, x7=7 -> x5=27».
Understand this scenario with real code like «add x5, x6, x7 # RV32I/RV64I: x6=20, x7=7 -> x5=27».
No. Base integer addition ignores arithmetic overflow; software must add explicit checks when overflow detection is required.
Use ADD when both operands are registers. Use ADDI when the second operand is a sign-extended 12-bit immediate.