Add rs1 and rs2, place result in rd
ADD is an R-type instruction in the RISC-V RV32I/RV64I base integer set. Its assembly syntax is `add rd, rs1, rs2` — it adds the values in registers rs1 and rs2 and writes the result to rd. Overflow is silently ignored; only the lower XLEN bits are kept (32-bit result on RV32, 64-bit on RV64). ADD uses opcode 0110011 with funct3=000 and funct7=0000000. For immediate addition, use ADDI instead.
ADD uses opcode 0110011 (0x33), funct3 000, funct7 0000000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
ADD (R-type) adds rs1 and rs2 (overflow ignored, low XLEN bits retained), writing to rd. funct7=0000000, funct3=000. The most fundamental arithmetic operation in RISC-V. Paired with ADDI for base+offset address computations.
ADD is register-to-register integer addition. In RV32I/RV64I semantics it adds rs1 and rs2, writes rd, does not trap on arithmetic overflow, and keeps the XLEN-wide result.
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Integer addition keeps only the low XLEN bits of the result; arithmetic overflow does not raise an exception. Software must add explicit checks when overflow detection is required.
RISC-V Unprivileged ISA, RV32I integer computational instructionsADD is an R-type instruction. Both operands come from rs1 and rs2, and the result is written to rd. Use ADDI for immediate addition.
RISC-V Unprivileged ISA, RV32I integer computational instructionsADD takes two register operands (rs1 + rs2), while ADDI takes one register and a 12-bit signed immediate (rs1 + imm). ADD is an R-type instruction (opcode 0110011); ADDI is I-type (opcode 0010011). If you need to add a constant outside the -2048 to 2047 range, load it into a temporary register first (using LUI+ADDI) and then use ADD.
ADD and SUB are both R-type instructions sharing the same opcode (0110011) and funct3 (000). They are distinguished solely by the funct7 field: ADD uses funct7 = 0000000 while SUB uses funct7 = 0100000. In other words, bit 30 of the instruction word selects between addition (bit30=0) and subtraction (bit30=1). RISC-V designed it this way to simplify decode logic and avoid wasting extra opcode space.
Understand this scenario with real code like «add x5, x6, x7 # x5 = x6 + x7».
Understand this scenario with real code like «add x5, x6, x7 # x5 = x6 + x7».
Understand this scenario with real code like «add x5, x6, x7 # x5 = x6 + x7».
No. Base integer addition ignores arithmetic overflow; software must add explicit checks when overflow detection is required.
Use ADD when both operands are registers. Use ADDI when the second operand is a sign-extended 12-bit immediate.