Add sign-extended 12-bit immediate to rs1, place result in rd
ADDI uses opcode 0010011 (0x13), funct3 000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
ADDI (I-type, opcode=0010011, funct3=000) adds the sign-extended 12-bit immediate to rs1 (overflow ignored, low XLEN bits retained) and writes to rd. ADDI x0,x0,0 is the canonical NOP encoding. ADDI rd,x0,imm loads a small immediate (pseudo LI). ADDI rd,rs1,0 copies a register (pseudo MV).
ADDI adds a sign-extended 12-bit immediate to rs1 and writes rd. It is the common base form for small constants, stack adjustment, address offsets, and move-like pseudo-instructions.
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Integer addition keeps only the low XLEN bits of the result; arithmetic overflow does not raise an exception. Software must add explicit checks when overflow detection is required.
RISC-V Unprivileged ISA, RV32I integer computational instructionsADDI adds a sign-extended 12-bit immediate to rs1. The encodable range is -2048 to 2047; larger constants are usually formed with LUI/AUIPC plus ADDI or the li pseudo-instruction.
RISC-V Unprivileged ISA, RV32I integer computational instructionsUnderstand this scenario with real code like «addi x5, x6, 100 # x5 = x6 + 100».
Understand this scenario with real code like «addi x5, x6, 100 # x5 = x6 + 100».
Understand this scenario with real code like «addi x5, x6, 100 # x5 = x6 + 100».
Understand this scenario with real code like «addi x5, x6, 100 # x5 = x6 + 100».
ADDI uses a sign-extended 12-bit immediate, typically -2048 to 2047. Larger constants require sequences such as LUI/AUIPC plus ADDI.
No separate SUBI exists in the base integer set. Subtract a small constant by using ADDI with a negative immediate.