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LUI

RISC-V LUI Instruction Details

Instruction ManualU-type

Place the U-immediate in result bits 31:12, clear bits 11:0, and write rd

Instruction Syntax

lui rd, imm
Operand Breakdown
Destination rd: register receiving the result.
Upper immediate: 20-bit value loaded into bits [31:12] of rd. Lower 12 bits are zero-filled.
RV32IRV64IImmediates & ConstantsAddress Computation
Related Search Terms
LUI instructionRISC-V LUIlui syntaxlui encodinglui U-typeImmediates & ConstantsLUI vs AUIPC

Instruction Behavior

LUI uses the U-type format (opcode=0110111). Encoded imm[31:12] forms a 32-bit U-immediate: bits 31:12 come from that field and bits 11:0 are zero, then the result is written to rd. In RV64I, this 32-bit result is sign-extended to 64 bits. LUI commonly helps construct larger constants; an LUI encoding with rd=x0 is standard HINT space and does not change x0.

LUI Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
imm20
lui
,
Execution Context
31..12
11..7
6..0
00010010001101000101
imm[31:12]
00101
rd
0110111
opcode
Execution Data Path
instruction
0x123452B7
opcode
0110111 -> LUI
rd
t0(x5)
imm[31:12]
00010010001101000101 << 12 -> 0x12345000
upper load
0x12345000
x5
t0(x5) = 0x12345000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x123452B7
syntax : lui t0(x5), 0x12345
result : t0(x5) = 0x12345000
Architectural Result
t0(x5) = 0x12345000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

LUI places the U-immediate into the upper portion of rd and clears the low 12 bits, commonly as the first step when forming larger constants.

The U-type immediate corresponds to the upper 20 bits of the result; the low 12 bits are zero.
On RV64I, the 32-bit LUI result is sign-extended to 64 bits.
RISC-V Unprivileged ISA Manual: RV32I Base Integer Instruction SetRISC-V Unprivileged ISA Manual: RV64I Base Integer Instruction Set

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Immediates & Constants

Understand this scenario with real code like «lui x5, 0x12345 # x5 = 0x12345 << 12 = 0x12345000».

Pre-Use Checklist

Syntax Check
  • Verify the upper 20-bit immediate (imm[31:12]) value is correct.
Semantic Check
  • Confirm usage with LUI for loading the upper 20 bits.
  • Ensure rd is not x0 (unless intentionally writing to zero register).

Pitfalls / Common Confusions

The lower 12 bits are always zero; constructing a value with nonzero low 12 bits generally needs a following instruction
In RV64I, a 32-bit LUI result whose bit 31 is 1 is sign-extended to 64 bits

FAQ

Can LUI load a full 32-bit constant by itself?

No. LUI sets the upper 20 bits and clears the low 12 bits; a full constant usually needs a following instruction such as ADDI.

What is the key difference between LUI and AUIPC?

LUI forms a value from the immediate alone; AUIPC adds the upper-immediate offset to the current PC.