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LUI

RISC-V LUI Instruction Details

Instruction ManualU-type

Place the U-immediate in result bits 31:12, clear bits 11:0, and write rd

Instruction Syntax

lui rd, imm
Operand Breakdown
rd: receives the XLEN-bit immediate result without reading old rd; rd=x0 is a HINT.
imm: the 20-bit field specifies bits 31:12; assembly omits the always-zero low 12 bits.
RV64 sign-extends the 32-bit result to 64 bits; when bit 31 is one, the upper 32 bits are all ones.
RV32IRV64IImmediates & ConstantsAddress Computation
Related Search Terms
LUI instructionRISC-V LUIlui syntaxlui encodinglui U-typeImmediates & ConstantsLUI vs AUIPC

Instruction Behavior

LUI uses the U-type format (opcode=0110111). Encoded imm[31:12] forms a 32-bit U-immediate: bits 31:12 come from that field and bits 11:0 are zero, then the result is written to rd. In RV64I, this 32-bit result is sign-extended to 64 bits. LUI commonly helps construct larger constants; an LUI encoding with rd=x0 is standard HINT space and does not change x0.

LUI Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
imm20
lui
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

31..12
11..7
6..0
00010010001101000101
imm[31:12]
00101
rd
0110111
opcode
Execution Data Path
instruction
0x123452B7
opcode
0110111 -> LUI
rd
t0(x5)
imm[31:12]
00010010001101000101 << 12 -> 0x12345000
upper load
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x123452B7
syntax : lui t0(x5), 0x12345
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

LUI places the 20-bit field in bits 31:12 and clears the low 12 bits; RV64 then sign-extends this 32-bit result to 64 bits.

The U-type 20-bit immediate field corresponds to result bits 31:12; the low 12 bits are zero.
On RV64I, the 32-bit LUI result is sign-extended to 64 bits.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (20260120), §2.4, §4.2.1The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (20260120), §2.4, §4.2.1

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Immediates & Constants

Understand this scenario with real code like «lui x5, 0x12345 # x5 = 0x12345 << 12 = 0x12345000».

Pre-Use Checklist

Syntax Check
  • Syntax is rd, imm; the 20-bit field specifies bits 31:12, with no rs1.
Semantic Check
  • Low 12 bits are zero; RV64 sign-extends the 32-bit result to 64 bits, and rd=x0 is a HINT.

Pitfalls / Common Confusions

The lower 12 bits are always zero; constructing a value with nonzero low 12 bits generally needs a following instruction
In RV64I, a 32-bit LUI result whose bit 31 is 1 is sign-extended to 64 bits

FAQ

Can LUI load a full 32-bit constant by itself?

It can form 32-bit values whose low 12 bits are zero. Other values need a following instruction for the low bits. RV64 also sign-extends the 32-bit LUI result.

What is the key difference between LUI and AUIPC?

LUI forms a value from the immediate alone; AUIPC adds the upper-immediate offset to the current PC.