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AUIPC

RISC-V AUIPC Instruction Details

Instruction ManualU-type

Add the 32-bit U-immediate offset to this instruction's PC; RV64 sign-extends the offset before writing rd

Instruction Syntax

auipc rd, imm
Operand Breakdown
rd: receives the XLEN-bit PC-plus-offset result; rd=x0 discards the writeback.
imm: specifies the 20-bit field at bits [31:12]; append 12 zero bits to form a 32-bit offset and sign-extend it to XLEN on RV64.
The PC base is this AUIPC instruction's address; the result's low 12 bits need not be zero.
RV32IRV64IAddress Computation
Related Search Terms
AUIPC instructionRISC-V AUIPCauipc syntaxauipc encodingauipc U-typeAUIPC address computationauipc pc relative

Instruction Behavior

AUIPC uses U-type encoding (opcode=0010111). Its assembly operand is a 20-bit U-immediate: append 12 zero bits to form a 32-bit offset, sign-extend that offset to 64 bits on RV64, and add it to the address of the AUIPC instruction itself. Write the low XLEN bits to rd. AUIPC itself neither jumps nor accesses data memory. With a JALR or load/store 12-bit offset, RV32 can cover 32-bit PC-relative addresses; the combined RV64 offset range is [-2^31-2^11, 2^31-2^11-1].

AUIPC Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
imm20
auipc
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

PC
0x00002000
31..12
11..7
6..0
00000000000000010000
imm[31:12]
00101
rd
0010111
opcode
Execution Data Path
instruction
0x00010297
opcode
0010111 -> AUIPC
rd / pc
t0(x5) / 0x00002000
imm[31:12]
00000000000000010000 << 12 -> 0x00010000
PC add
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00010297
syntax : auipc t0(x5), 0x10
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

AUIPC adds this instruction's PC to the offset formed from the U-immediate. RV64 first sign-extends the 32-bit offset to XLEN. It forms an address and commonly pairs with JALR or loads/stores.

AUIPC uses the PC of the AUIPC instruction itself, not the next instruction.
AUIPC plus JALR forms a PC-relative control-transfer sequence.
The U-immediate specifies bits [31:12]; append 12 zero bits and sign-extend the resulting offset on RV64.
rd=x0 discards the result; AUIPC itself performs no control transfer or data-memory access.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120: Official Release

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Address & Pointer

RV32I/RV64I, PC=0x2000: auipc x5, 0x1000 gives x5=0x01002000; it only forms a register address value, with no jump or data-memory access.

Immediates & Constants

RV32I/RV64I, PC=0x2000: auipc x5, 0x1000 gives x5=0x01002000; it only forms a register address value, with no jump or data-memory access.

Pre-Use Checklist

Syntax Check
  • Verify the upper 20-bit immediate (imm[31:12]) value is correct.
Semantic Check
  • Confirm usage with subsequent instructions for PC-relative addressing.
  • Ensure rd is not x0 (unless intentionally writing to zero register).

Pitfalls / Common Confusions

The PC base is the address of the AUIPC instruction itself, not the next instruction.
The offset has 12 low zero bits; after adding PC, rd inherits the low 12 bits of PC, which need not be zero.
RV64 sign-extends the 32-bit offset to XLEN; do not treat it as a zero-extended positive value.

FAQ

Which PC does AUIPC use?

The official semantics use the address of the AUIPC instruction itself as the PC base.

Which instructions commonly pair with AUIPC?

It commonly pairs with JALR for PC-relative jumps, or with load/store 12-bit offsets for PC-relative data access.