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AUIPC

RISC-V AUIPC Instruction Details

Instruction ManualU-type

Add a 20-bit upper immediate (shifted left 12 bits) to the PC and place the result in rd

Instruction Syntax

auipc rd, imm
Operand Breakdown
Destination rd: register receiving the result.
Upper immediate: 20-bit value loaded into bits [31:12] of rd. Lower 12 bits are zero-filled.
RV32IControl TransferAddress Computation
Related Search Terms
AUIPC instructionRISC-V AUIPCauipc syntaxauipc encodingauipc U-typeAddress Computationauipc pc relative

Instruction Encoding

31..12
imm[31:12]
11..7
rd
6..0
opcode

AUIPC uses opcode 0010111 (0x17). The 20-bit immediate is loaded into the upper 20 bits of rd, with lower 12 bits zero-filled.

Format: U-type
opcode: 0010111 (0x17)

Instruction Behavior

AUIPC (U-type, opcode=0010111) forms a 32-bit offset from the U-immediate (filling lower 12 bits with zeros), adds this offset to the address of the AUIPC instruction itself, and places the result in rd. Key for PC-relative addressing: paired with JALR for arbitrary PC-relative control transfers, or with load/store 12-bit offsets for arbitrary PC-relative data access.

Quick Understanding & Search Notes

AUIPC forms a PC-relative address by adding the current instruction address to the U-immediate shifted left 12 bits. It is commonly paired with JALR or loads/stores.

AUIPC uses the PC of the AUIPC instruction itself, not the next instruction.
AUIPC plus JALR forms a PC-relative control-transfer sequence.
RISC-V Unprivileged ISA Manual: RV32I Base Integer Instruction Set

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «auipc x5, 0x1000 # x5 = pc + (0x1000 << 12)».

Immediates & Constants

Understand this scenario with real code like «auipc x5, 0x1000 # x5 = pc + (0x1000 << 12)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is U-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Lower 12 bits are always zero — the U-immediate only specifies bits [31:12]
Unlike LUI, AUIPC result depends on code position (the instruction's own PC), making it suitable for PIC — but not for position-independent constants

FAQ

Which PC does AUIPC use?

The official semantics use the address of the AUIPC instruction itself as the PC base.

Which instructions commonly pair with AUIPC?

It commonly pairs with JALR for PC-relative jumps, or with load/store 12-bit offsets for PC-relative data access.