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AUIPC

RISC-V AUIPC Instruction Details

Instruction ManualU-type

Add a 20-bit upper immediate (shifted left 12 bits) to the PC and place the result in rd

Instruction Syntax

auipc rd, imm
Operand Breakdown
Destination rd: register receiving the result.
Upper immediate: 20-bit value loaded into bits [31:12] of rd. Lower 12 bits are zero-filled.
RV32IControl TransferAddress Computation
Related Search Terms
AUIPC instructionRISC-V AUIPCauipc syntaxauipc encodingauipc U-typeAddress Computationauipc pc relative

Instruction Behavior

AUIPC (U-type, opcode=0010111) forms a 32-bit offset from the U-immediate (filling lower 12 bits with zeros), adds this offset to the address of the AUIPC instruction itself, and places the result in rd. Key for PC-relative addressing: paired with JALR for arbitrary PC-relative control transfers, or with load/store 12-bit offsets for arbitrary PC-relative data access.

AUIPC Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
imm20
auipc
,
Execution Context
31..12
11..7
6..0
00000000000000010000
imm[31:12]
00101
rd
0010111
opcode
Execution Data Path
instruction
0x00010297
opcode
0010111 -> AUIPC
rd / pc
t0(x5) / 0x00002000
imm[31:12]
00000000000000010000 << 12 -> 0x00010000
PC add
0x00002000 + 0x00010000 = 0x00012000
x5
t0(x5) = 0x00012000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00010297
syntax : auipc t0(x5), 0x10
result : t0(x5) = 0x00012000
Architectural Result
t0(x5) = 0x00012000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

AUIPC forms a PC-relative address by adding the current instruction address to the U-immediate shifted left 12 bits. It is commonly paired with JALR or loads/stores.

AUIPC uses the PC of the AUIPC instruction itself, not the next instruction.
AUIPC plus JALR forms a PC-relative control-transfer sequence.
RISC-V Unprivileged ISA Manual: RV32I Base Integer Instruction Set

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «auipc x5, 0x1000 # x5 = pc + (0x1000 << 12)».

Immediates & Constants

Understand this scenario with real code like «auipc x5, 0x1000 # x5 = pc + (0x1000 << 12)».

Pre-Use Checklist

Syntax Check
  • Verify the upper 20-bit immediate (imm[31:12]) value is correct.
Semantic Check
  • Confirm usage with subsequent instructions for PC-relative addressing.
  • Ensure rd is not x0 (unless intentionally writing to zero register).

Pitfalls / Common Confusions

Lower 12 bits are always zero; the U-immediate only specifies bits [31:12]
Unlike LUI, AUIPC depends on code position because it uses the address of the AUIPC instruction itself as its PC base.

FAQ

Which PC does AUIPC use?

The official semantics use the address of the AUIPC instruction itself as the PC base.

Which instructions commonly pair with AUIPC?

It commonly pairs with JALR for PC-relative jumps, or with load/store 12-bit offsets for PC-relative data access.