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JAL

RISC-V JAL Instruction Details

Instruction ManualJ-type

Jump to PC-relative offset, storing return address (PC+4) in rd

Instruction Syntax

jal rd, offset
Operand Breakdown
Destination rd: register for return address (pc+4). Set to x0 to skip saving.
Immediate offset: signed 21-bit byte offset with implicit bit 0=0; encodable even values range from -1048576 through 1048574.
RV32IRV64IControl TransferJump
Related Search Terms
JAL instructionRISC-V JALjal syntaxjal encodingjal J-typeJAL vs JALRjal jump

Instruction Behavior

JAL uses J-type encoding (opcode=1101111). Its signed byte displacement is even and ranges from -1048576 through 1048574. The sign-extended displacement is added to the JAL address, wrapping to XLEN bits. Successful execution writes PC+4 to rd; rd=x0 discards the link write (pseudo J). rd=x1 or x5 supplies implicit RAS prediction hints. With IALIGN=32, a target not divisible by 4 raises an instruction-address-misaligned exception on JAL. With IALIGN=16, JAL's even targets cannot raise that exception.

JAL Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
offset
jal
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

PC
0x00002000
31..12
11..7
6..0
0 0010000000 0 00000000
imm[20|10:1|11|19:12]
00001
rd
1101111
opcode
Execution Data Path
instruction
0x100000EF
opcode
1101111 -> JAL
rd / pc
ra(x1) / 0x00002000
J-imm
reassembled offset 256
target/link
Not computed
PC / link
ra(x1) = 0x00002004; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x100000EF
syntax : jal x1, 256
Pending result: Not computed
Current architectural state
ra(x1) = 0x00002004; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

JAL is a PC-relative jump-and-link: the target is the J-type offset plus the current PC, and pc+4 is written to rd. With rd=x0, it jumps without saving a return address.

The J-type byte displacement has an implicit zero low bit; its even encodable range is -1048576 through 1048574.
Calls typically use ra as rd; unconditional jumps typically use x0 as rd.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Official Release 20260120, §2.5.1

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Branch & Jump

RV32I/RV64I, IALIGN=32 example: at PC=0x2000, jal ra, 256 successfully jumps to 0x2100 and sets ra=0x2004.

Function Call & Return

RV32I/RV64I, IALIGN=32 example: at PC=0x2000, jal ra, 256 successfully jumps to 0x2100 and sets ra=0x2004.

Pre-Use Checklist

Syntax Check
  • Register operands select x0 through x31; ABI register names are aliases for those registers.
  • JAL rd may be any of x0 through x31; x1/x5 are convention and implicit RAS-hint choices, not legality restrictions.
  • The byte displacement must be even and range from -1048576 through 1048574; bit 0 is implicitly zero.
Semantic Check
  • The target is old PC plus displacement, truncated to XLEN. IALIGN=32 requires a multiple of 4; IALIGN=16 requires a multiple of 2.
  • A successful jump writes old PC+4 to rd; x0 writes are discarded. A target misaligned for IALIGN=32 raises an exception on JAL.

Pitfalls / Common Confusions

JAL offsets are encoded in 2-byte units; whether a 4-byte-aligned target is required depends on the implementation IALIGN
Return address is PC+4 (instruction length), not PC (current instruction address)
The encodable byte displacement is even and ranges from -1048576 through 1048574; a farther target cannot be encoded directly in one JAL

FAQ

What return address does JAL save?

JAL writes the next instruction address, pc+4, into rd.

When should I use JAL vs JALR?

Use JAL for a direct PC-relative target nearby. Use JALR when the target comes from a register or from an AUIPC+JALR sequence.