Link Address
JAL writes the address of the next instruction (pc+4) to rd. With rd=x0, no return address is saved, so it acts as an unconditional jump.
RISC-V Unprivileged ISA, RV32I control transfer instructionsJAL
RISC-V JAL Instruction Details
Instruction ManualJ-typeJump to PC-relative offset, storing return address (PC+4) in rd
Instruction Syntax
jal rd, offset
Operand Breakdown
Destination rd: register for return address (pc+4). Set to x0 to skip saving.
Immediate offset: 21-bit signed jump offset (±1 MiB range).
RV32IControl TransferJump
Related Search Terms
Instruction Behavior
JAL uses the J-type format (opcode=1101111), where the J-immediate encodes a signed offset in multiples of 2 bytes. The offset is sign-extended and added to the JAL instruction address, yielding a ±1 MiB range. JAL stores PC+4 into rd. When rd=x0, it acts as an unconditional jump (pseudo J). When rd=x1 or x5, hardware may use RAS prediction. An instruction-address-misaligned exception is raised on a misaligned target.
JAL Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
offset
jal
,
Execution Context
31..12
11..7
6..0
0 0010000000 0 00000000
imm[20|10:1|11|19:12]
00001
rd
1101111
opcode
Execution Data Path
instruction
0x100000EF
opcode
1101111 -> JAL
rd / pc
ra(x1) / 0x00002000
J-imm
reassembled offset 256
target/link
link=0x00002004, target=0x00002100
PC / link
ra(x1) = 0x00002004; pc = 0x00002100
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x100000EF
syntax : jal ra(x1), 256
result : ra(x1) = 0x00002004; pc = 0x00002100
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
JAL is a PC-relative jump-and-link: the target is the J-type offset plus the current PC, and pc+4 is written to rd. With rd=x0, it jumps without saving a return address.
The J-type offset is encoded in 2-byte units and has an approximate +/-1 MiB reach.
Calls typically use ra as rd; unconditional jumps typically use x0 as rd.
Official Spec Notes
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Jump Range
The J-type immediate encodes a signed PC-relative offset in 2-byte units, giving JAL an approximate reach of +/-1 MiB from the current PC.
RISC-V Unprivileged ISA, RV32I control transfer instructionsCommon Usage Scenarios
Branch & Jump
Understand this scenario with real code like «jal x1, 0x100 # jump to pc+0x100, x1 = pc+4».
Function Call & Return
Understand this scenario with real code like «jal x1, 0x100 # jump to pc+0x100, x1 = pc+4».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is J-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
JAL offsets are encoded in 2-byte units; whether a 4-byte-aligned target is required depends on the implementation IALIGN
Return address is PC+4 (instruction length), not PC (current instruction address)
Range is ±1 MiB; use indirect jumps if beyond range
FAQ
What return address does JAL save?
JAL writes the next instruction address, pc+4, into rd.
When should I use JAL vs JALR?
Use JAL for a direct PC-relative target nearby. Use JALR when the target comes from a register or from an AUIPC+JALR sequence.