Target Address Calculation
JALR forms the target from rs1 plus a sign-extended 12-bit immediate, then clears the least-significant bit of the target address before jumping.
RISC-V Unprivileged ISA, RV32I control transfer instructionsJALR
RISC-V JALR Instruction Details
Instruction ManualI-typeJump to rs1 + sign-extended 12-bit immediate (LSB cleared), storing return address in rd
Instruction Syntax
jalr rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IControl TransferJump
Instruction Behavior
JALR (I-type, opcode=1100111, funct3=000) computes the target address as rs1 + sign-extended 12-bit immediate, with the LSB always cleared to zero. PC+4 is stored in rd. When rd=x0, it acts as an indirect jump (pseudo JR). When rd=x0, rs1=x1, imm=0, it is a return (pseudo RET). LSB clearing simplifies hardware and allows auxiliary info in function pointer LSB. rd/rs1 combinations of x1/x5 provide implicit RAS hints.
JALR Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
imm
rs1
jalr,()
Execution Context
31..20
19..15
14..12
11..7
6..0
000000000000
imm[11:0]
00101
rs1
000
funct3
00001
rd
1100111
opcode
Execution Data Path
instruction
0x000280E7
opcode
1100111 -> JALR
funct3
000 -> JALR
rd / rs1 / pc
ra(x1) / t0(x5)=0x00003001 / 0x00002000
imm[11:0]
000000000000 -> 0
target/link
link=0x00002004, (0x00003001 & ~1)=0x00003000
PC / link
ra(x1) = 0x00002004; pc = 0x00003000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x000280E7
syntax : jalr ra(x1), 0(t0(x5))
result : ra(x1) = 0x00002004; pc = 0x00003000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
JALR is register-indirect jump-and-link: the target is rs1 plus a sign-extended 12-bit immediate, with bit 0 cleared before jumping, and pc+4 written to rd.
JALR immediate is not scaled by 2; it is a normal signed 12-bit byte offset.
Clearing bit 0 permits auxiliary information in function-pointer low bits and simplifies hardware.
Official Spec Notes
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Return Address Writeback
Like JAL, JALR writes pc+4 to rd. The ret pseudo-instruction commonly expands to jalr x0, 0(ra), so it does not write a link register.
RISC-V Unprivileged ISA, RV32I control transfer instructionsCommon Usage Scenarios
Address & Pointer
Understand this scenario with real code like «jalr x1, 0(x5) # jump to x5, x1 = pc+4».
Function Call & Return
Understand this scenario with real code like «jalr x1, 0(x5) # jump to x5, x1 = pc+4».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Target address bit 0 is cleared, but this does not guarantee 4-byte alignment; misaligned-target behavior still depends on the target address and IALIGN
Immediate is not encoded in multiples of 2 (unlike branches which encode offset >> 1)
rd and rs1 combinations of x1/x5 provide implicit RAS hints; misusing them degrades branch prediction
FAQ
Why does JALR clear the target address low bit?
The official manual says this simplifies hardware and allows auxiliary information in the low bit of function pointers.
What does RET commonly expand to?
A common return form is jalr x0, 0(ra): it writes no return address and jumps to the address in ra.