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JALR

RISC-V JALR Instruction Details

Instruction ManualI-type

Jump to rs1 + sign-extended 12-bit immediate (LSB cleared), storing return address in rd

Instruction Syntax

jalr rd, offset(rs1)
Operand Breakdown
rd: receives old PC+4 on a successful jump; rd=x0 discards writeback.
rs1: provides the jump base using its value before writeback.
imm: signed byte offset from -2048 through 2047; truncate rs1 plus sign-extended imm to XLEN, then clear bit 0. The target must also satisfy current IALIGN.
RV32IRV64IControl TransferJump
Related Search Terms
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Instruction Behavior

JALR (I-type, opcode=1100111, funct3=000) computes the target address as rs1 + sign-extended 12-bit immediate, with the LSB always cleared to zero. PC+4 is stored in rd. With rd=x0, it performs an indirect jump without saving a return address; the official manual describes the plain unconditional indirect-jump pseudoinstruction JR as a JALR with rd=x0. When rd=x0, rs1=x1, imm=0, it is a return (pseudo RET). LSB clearing simplifies hardware and allows auxiliary info in function pointer LSB. rd/rs1 combinations of x1/x5 provide implicit RAS hints.

JALR Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
imm
rs1
jalr
,
(
)
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

t0(x5)
0x00003001
PC
0x00002000
31..20
19..15
14..12
11..7
6..0
000000000000
imm[11:0]
00101
rs1
000
funct3
00001
rd
1100111
opcode
Execution Data Path
instruction
0x000280E7
opcode
1100111 -> JALR
funct3
000 -> JALR
rd / rs1 / pc
ra(x1) / t0(x5)=0x00003001 / 0x00002000
imm[11:0]
000000000000 -> 0
target/link
Not computed
PC / link
ra(x1) = 0x00002004; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x000280E7
syntax : jalr x1, 0(x5)
Pending result: Not computed
Current architectural state
ra(x1) = 0x00002004; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

JALR is register-indirect jump-and-link: the target is rs1 plus a sign-extended 12-bit immediate, with bit 0 cleared before jumping, and pc+4 written to rd.

JALR immediate is not scaled by 2; it is a normal signed 12-bit byte offset.
Clearing bit 0 permits auxiliary information in function-pointer low bits and simplifies hardware.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Official Release 20260120, §2.5.1

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Address & Pointer

RV32I/RV64I, IALIGN=32 example: with PC=0x2000 and ra=0x3001, jalr x0, 0(ra) successfully jumps to 0x3000; x0 remains zero.

Function Call & Return

RV32I/RV64I, IALIGN=32 example: with PC=0x2000 and ra=0x3001, jalr x0, 0(ra) successfully jumps to 0x3000; x0 remains zero.

Pre-Use Checklist

Syntax Check
  • Register operands select x0 through x31; ABI register names are aliases for those registers.
  • The signed 12-bit immediate encodes -2048 through 2047, including both endpoints.
Semantic Check
  • The target is rs1 plus the sign-extended byte offset, truncated to XLEN with bit 0 cleared; the target must also satisfy IALIGN.
  • A successful jump writes old PC+4 to rd, with x0 writes discarded; rs1 uses its value before writeback.

Pitfalls / Common Confusions

Target address bit 0 is cleared, but this does not guarantee 4-byte alignment; misaligned-target behavior still depends on the target address and IALIGN
Immediate is not encoded in multiples of 2 (unlike branches which encode offset >> 1)
rd and rs1 combinations of x1/x5 supply implicit RAS hints, without guaranteeing predictor behavior or performance

FAQ

Why does JALR clear the target address low bit?

The official manual says this simplifies hardware and allows auxiliary information in the low bit of function pointers.

What does RET commonly expand to?

The standard return form is jalr x0, 0(ra). Its target is the old ra value with bit 0 cleared (ra & ~1); the link write to x0 is discarded. With IALIGN=32, the target must also be divisible by 4 or an instruction-address-misaligned exception is raised.