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BEQ

RISC-V BEQ Instruction Details

Instruction ManualB-type

Branch to PC-relative offset if rs1 equals rs2

Instruction Syntax

beq rs1, rs2, offset
Operand Breakdown
Source rs1: first comparison operand.
Source rs2: second comparison operand.
Immediate offset: 13-bit signed branch offset (bit 0 is implicitly 0, ±4 KiB range).
RV32IRV64IControl TransferBranch
Related Search Terms
BEQ instructionRISC-V BEQbeq syntaxbeq encodingbeq B-typeBEQ vs BNEbeq branch

Instruction Behavior

BEQ (B-type, opcode=1100011, funct3=000) branches when the XLEN-bit patterns in rs1 and rs2 are equal. Twelve encoded immediate bits plus implicit bit 0=0 form a signed 13-bit byte offset: even values from -4096 through 4094, added to the current BEQ PC. Only a taken target violating IALIGN raises instruction-address-misaligned; an untaken branch continues at PC+4.

BEQ Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1
rs2
offset
beq
,
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

t2(x7)
0x00000007
PC
0x00002000
31..25
24..20
19..15
14..12
11..7
6..0
0 000000
imm[12|10:5]
00111
rs2
00111
rs1
000
funct3
1000 0
imm[4:1|11]
1100011
opcode
Execution Data Path
instruction
0x00738863
opcode
1100011 -> BRANCH
funct3
000 -> BEQ
rs1 / rs2 / pc
t2(x7)=0x00000007 / t2(x7)=0x00000007 / 0x00002000
B-imm
reassembled offset 16; bit 0 is implicit 0
condition
Not computed
PC
pc = 0x00002000; general registers unchanged
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00738863
syntax : beq x7, x7, 16
Pending result: Not computed
Current architectural state
pc = 0x00002000; general registers unchanged

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

BEQ is a conditional branch: when rs1 and rs2 satisfy the equal condition, the PC branches to the current PC plus the B-type offset; otherwise execution falls through.

The B-type byte offset has implicit bit 0=0 and encodes even values from -4096 through 4094; the target is the current branch PC plus the sign-extended offset.
RISC-V conditional branches do not write rd or save a return address; only a taken target that violates IALIGN raises an instruction-address-misaligned exception.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120, §2.5.2

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «beq x1, x2, target # branch to target if x1 == x2».

Pre-Use Checklist

Syntax Check
  • Register operands select x0 through x31; ABI register names are aliases for these registers.
  • B-type byte offsets are even values from -4096 through 4094, with implicit bit 0=0.
Semantic Check
  • BEQ tests bit-pattern equality; BLT/BGE compare signed integers, and BGEU compares unsigned integers.
  • A taken aligned branch updates PC to the current PC plus offset; an untaken branch continues at PC+4. General registers are unchanged, and only a taken target violating IALIGN raises instruction-address-misaligned.

Pitfalls / Common Confusions

B-type byte offsets are even values from -4096 through 4094; farther control transfers require another instruction sequence.
Conditional branches have no architecturally visible delay slot.
B-type targets are encoded in 2-byte units; only a taken target violating IALIGN raises instruction-address-misaligned, which cannot occur with IALIGN=16.

FAQ

What is the BEQ branch range?

B-type encodes even byte offsets from -4096 through 4094, added to the current branch PC. A taken target must also be a multiple of 4 for IALIGN=32; two-byte alignment suffices for IALIGN=16.

What is the difference between signed and unsigned branches?

BLT/BGE compare as signed integers; BLTU/BGEU compare as unsigned integers. BEQ/BNE only test equality of the bit patterns.