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BGEU

RISC-V BGEU Instruction Details

Instruction ManualB-type

Branch if rs1 is greater than or equal to rs2 (unsigned comparison)

Instruction Syntax

bgeu rs1, rs2, offset
Operand Breakdown
Source rs1: first comparison operand.
Source rs2: second comparison operand.
Immediate offset: 13-bit signed branch offset (bit 0 is implicitly 0, ±4 KiB range).
RV32IRV64IControl TransferBranch
Related Search Terms
BGEU instructionRISC-V BGEUbgeu syntaxbgeu encodingbgeu B-typeBGEU vs BGEbgeu branch

Instruction Behavior

BGEU compares rs1 and rs2 as unsigned integers and branches if rs1 >= rs2 (range ±4 KiB). BLEU can be synthesized by swapping BGEU operands. BLTU is the logical inverse. It is commonly used for address comparison and memory range checking. An instruction-address-misaligned exception occurs only when the branch is taken and its target violates IALIGN.

BGEU Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1
rs2
offset
bgeu
,
,
Execution Context
s1(x9)
0x00000009
PC
0x00002000
31..25
24..20
19..15
14..12
11..7
6..0
0 000000
imm[12|10:5]
00100
rs2
01001
rs1
111
funct3
1000 0
imm[4:1|11]
1100011
opcode
Execution Data Path
instruction
0x0044F863
opcode
1100011 -> BRANCH
funct3
111 -> BGEU
rs1 / rs2 / pc
s1(x9)=0x00000009 / tp(x4)=0x00000004 / 0x00002000
B-imm
reassembled offset 16; bit 0 is implicit 0
condition
>= -> taken; IALIGN=32: aligned target
PC
pc = 0x00002010 (target)
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x0044F863
syntax : bgeu s1(x9), tp(x4), 16
result : pc = 0x00002010 (target)
Architectural Result
pc = 0x00002010 (target)

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

BGEU is a conditional branch: when rs1 and rs2 satisfy the unsigned greater than or equal condition, the PC branches to the current PC plus the B-type offset; otherwise execution falls through.

The B-type branch offset is encoded in 2-byte units and reaches about +/-4 KiB from the current PC.
RISC-V conditional branches do not write rd or save a return address; only a taken target that violates IALIGN raises an instruction-address-misaligned exception.
RISC-V Unprivileged ISA Manual: RV32I/RV64I Base Integer Instruction Set

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «bgeu x11, x12, valid # if x11 >= x12 (unsigned), go to valid».

Comparison & Detection

Understand this scenario with real code like «bgeu x11, x12, valid # if x11 >= x12 (unsigned), go to valid».

Pre-Use Checklist

Syntax Check
  • Verify the branch target is within ±4 KiB range.
  • Confirm the comparison condition (eq/ne/lt/ge/ltu/geu) matches intent.
Semantic Check
  • Check if branch prediction direction impacts performance hotspots.
  • Note B-type immediate uses non-contiguous encoding (bit 0 is implicitly 0).

Pitfalls / Common Confusions

Use BGE for signed comparison
BLEU synthesized by reversing BGEU operands
Only a taken target that violates IALIGN raises instruction-address-misaligned; a not-taken branch does not

FAQ

What is the BGEU branch range?

Conditional branches use a B-type immediate, giving an approximate reach of +/-4 KiB from the current PC.

What is the difference between signed and unsigned branches?

BLT/BGE compare as signed integers; BLTU/BGEU compare as unsigned integers. BEQ/BNE only test equality of the bit patterns.