Is the immediate zero-extended?
No. Its encodable range is −2048 through 2047 and it is sign-extended to XLEN. For example, ori x5, x6, -1 writes all XLEN bits of x5 as ones.
ORI
RISC-V ORI Instruction Details
Instruction ManualI-typeBitwise OR rs1 with a sign-extended 12-bit immediate and write rd.
Instruction Syntax
ori rd, rs1, imm
Operand Breakdown
RV32I/RV64I; 32-bit I-type, opcode=0010011 and funct3=110.
rd=[11:7] and rs1=[19:15] select x0–x31; imm=[31:20] is a signed 12-bit immediate, −2048..2047.
Sign-extend imm to XLEN, then bitwise OR with old rs1. Negative immediates have upper bits set.
rd may overlap rs1; rd=x0 discards writeback. Nonnegative immediates can set encodable low mask bits.
RV32IRV64ILogical
Related Search Terms
Instruction Behavior
ORI is a 32-bit I-type instruction in RV32I/RV64I. Sign-extend the immediate, from −2048 through 2047, to XLEN, OR it with the old rs1, and write rd; rd=x0 discards the write. Nonnegative immediates can set low mask bits. Negative immediates also OR upper bits with ones, so the operand is not an arbitrary zero-extended 12-bit mask.
ORI Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
imm
ori
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x00000014
31..20
19..15
14..12
11..7
6..0
000000001111
imm[11:0]
00110
rs1
110
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x00F36293
opcode
0010011 -> OP-IMM
funct3
110 -> ORI bitwise OR
rd / rs1
t0(x5) / t1(x6)
imm[11:0]
000000001111 -> sign_extend(15)=0x0000000F
bitwise ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00F36293
syntax : ori t0(x5), t1(x6), 15
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
Bit-by-Bit Logic View
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sign-extended imm
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Bitwise OR rs1 with a sign-extended 12-bit immediate and write rd.
opcode=0010011 selects OP-IMM, and funct3=110 selects ORI.
The I-type imm[11:0] is sign-extended to XLEN; an immediate with its sign bit set ORs upper bits with ones.
Common Usage Scenarios
Bit Operations & Masks
RV32I/RV64I, old x6=20: ori x5, x6, 15 writes x5=31 (0x1f). Immediate 15 is encodable and its positive sign extension adds zero upper bits.
Immediates & Constants
RV32I/RV64I, old x6=20: ori x5, x6, 15 writes x5=31 (0x1f). Immediate 15 is encodable and its positive sign extension adds zero upper bits.
Register Operations
RV32I/RV64I, old x6=20: ori x5, x6, 15 writes x5=31 (0x1f). Immediate 15 is encodable and its positive sign extension adds zero upper bits.
Pre-Use Checklist
Syntax Check
- RV32I/RV64I; 32-bit I-type, opcode=0010011 and funct3=110.
- rd=[11:7] and rs1=[19:15] select x0–x31; imm=[31:20] is a signed 12-bit immediate, −2048..2047.
Semantic Check
- Sign-extend imm to XLEN, then bitwise OR with old rs1. Negative immediates have upper bits set.
- rd may overlap rs1; rd=x0 discards writeback. Nonnegative immediates can set encodable low mask bits.
Pitfalls / Common Confusions
Immediate is 12-bit signed; sign extension of negative values may produce unexpected upper bits
FAQ
Can rd overlap rs1 or be x0?
Yes. Read the old rs1 before writeback when they overlap. With rd=x0 the write is discarded and x0 remains zero.