Is the immediate zero-extended?
ORI immediate forms use a 12-bit signed immediate that is sign-extended to XLEN.
ORI
RISC-V ORI Instruction Details
Instruction ManualI-typeBitwise OR of rs1 with sign-extended 12-bit immediate, result in rd
Instruction Syntax
ori rd, rs1, imm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32ILogical
Related Search Terms
Instruction Behavior
ORI performs bitwise OR of rs1 with the sign-extended 12-bit immediate, writing to rd. Commonly used to set specific bits (masking), merge register values with constants, and combine with LUI to construct arbitrary 32-bit constants.
ORI Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
imm
ori
,
,
Execution Context
31..20
19..15
14..12
11..7
6..0
000000001111
imm[11:0]
00110
rs1
110
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x00F36293
opcode
0010011 -> OP-IMM
funct3
110 -> ORI bitwise OR
rd / rs1
t0(x5) / t1(x6)
imm[11:0]
000000001111 -> sign_extend(15)=0x0000000F
bitwise ALU
0x00000014 | 0x0000000F = 0x0000001F
x5
t0(x5) = 0x0000001F
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00F36293
syntax : ori t0(x5), t1(x6), 15
result : t0(x5) = 0x0000001F
Bit-by-Bit Logic View
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sign-extended imm
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
ORI is an RV32I/RV64I OP-IMM logical-immediate instruction: imm[11:0] is sign-extended to XLEN, ORed bit by bit with rs1, and written to rd. It is useful for setting bits represented by the encodable immediate.
opcode=0010011 selects OP-IMM, and funct3=110 selects ORI.
The I-type imm[11:0] is sign-extended to XLEN; an immediate with its sign bit set ORs upper bits with ones.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «ori x5, x6, 0x0F # x5 = x6 | 0x0F».
Immediates & Constants
Understand this scenario with real code like «ori x5, x6, 0x0F # x5 = x6 | 0x0F».
Register Operations
Understand this scenario with real code like «ori x5, x6, 0x0F # x5 = x6 | 0x0F».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Immediate is 12-bit signed; sign extension of negative values may produce unexpected upper bits
FAQ
Does ori zero-extend the immediate before OR?
No. Like the ordinary I-type integer-immediate instructions, ORI sign-extends the 12-bit immediate before the operation.