Is the immediate zero-extended?
ORI immediate forms use a 12-bit signed immediate that is sign-extended to XLEN.
ORI
RISC-V ORI Instruction Details
Instruction ManualI-typeBitwise OR of rs1 with sign-extended 12-bit immediate, result in rd
Instruction Syntax
ori rd, rs1, imm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32ILogical
Related Search Terms
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
ORI uses opcode 0010011 (0x13), funct3 110. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0010011 (0x13)
funct3: 110 (0x6)
Instruction Behavior
ORI performs bitwise OR of rs1 with the sign-extended 12-bit immediate, writing to rd. Commonly used to set specific bits (masking), merge register values with constants, and combine with LUI to construct arbitrary 32-bit constants.
Quick Understanding & Search Notes
ORI is a base integer bitwise logical instruction. It operates across XLEN bits; immediate forms use a sign-extended 12-bit immediate.
The I-type immediate is sign-extended to XLEN before the bitwise operation.
Integer logical operations do not raise arithmetic-overflow exceptions; rd=x0 discards the result.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «ori x5, x6, 0x0F # x5 = x6 | 0x0F».
Immediates & Constants
Understand this scenario with real code like «ori x5, x6, 0x0F # x5 = x6 | 0x0F».
Register Operations
Understand this scenario with real code like «ori x5, x6, 0x0F # x5 = x6 | 0x0F».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Immediate is 12-bit signed; sign extension of negative values may produce unexpected upper bits
FAQ
Does it update flags?
The base integer ISA has no condition-code flags; only rd is written.