What is the difference between OR and ORI?
OR reads two registers, rs1 and rs2. ORI reads rs1 and uses a sign-extended 12-bit immediate.
OR
RISC-V OR Instruction Details
Instruction ManualR-typeBitwise OR of rs1 and rs2, result in rd
Instruction Syntax
or rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32ILogical
Related Search Terms
Instruction Behavior
OR (R-type) performs bitwise OR of rs1 and rs2, writing to rd. funct7=0000000, funct3=110. Used for setting bits (with masks), merging flag fields, and (less optimally) register moves with zero register.
OR Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
or
,
,
Execution Context
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11..7
6..0
0000000
funct7
00111
rs2
00110
rs1
110
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x007362B3
opcode
0110011 -> OP
funct3
110 -> OR bitwise OR
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / t2(x7)
immediate
not used
bitwise ALU
0x00000014 | 0x00000007 = 0x00000017
x5
t0(x5) = 0x00000017
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x007362B3
syntax : or t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000017
Bit-by-Bit Logic View
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
OR is an RV32I/RV64I base integer R-type logical instruction: it reads two XLEN-wide register values from rs1 and rs2, applies bitwise OR, and writes rd. It is useful for setting target bits selected by a mask or combining bit fields.
opcode=0110011 selects the OP class; funct3=110 with funct7=0000000 selects OR.
OR has no immediate field; use ORI for small immediate set-bit masks and OR for masks or fields already held in registers.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «or x5, x6, x7 # x5 = x6 | x7».
Register Operations
Understand this scenario with real code like «or x5, x6, x7 # x5 = x6 | x7».
Vector Operations
Understand this scenario with real code like «or x5, x6, x7 # x5 = x6 | x7».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
OR rd,rs,x0 works for copy but is suboptimal; MV is encoded as ADDI
FAQ
Is or rd, rs1, x0 the official mv form?
It produces the same register value, but the RISC-V Assembly Programmer's Manual commonly defines the mv pseudoinstruction as addi rd, rs1, 0.