RISC-V OR Instruction Details

Instruction ManualR-type

Bitwise OR of rs1 and rs2, result in rd

Instruction Syntax

or rd, rs1, rs2

Operand Breakdown

rd: receives the result; source/destination overlap uses old source values, and rd=x0 discards writeback.

rs1, rs2: the two XLEN-bit sources for bitwise OR; there is no immediate field.

Available on RV32I/RV64I; an x0 source is always zero.

RV32IRV64ILogical

Related Search Terms

OR instruction RISC-V OR or syntax or encoding or R-type or set bits bitwise OR

Instruction Behavior

OR uses the R-type encoding: it reads the XLEN-bit values in rs1 and rs2, performs a bitwise OR, and writes the result to rd. Its fixed fields are opcode=0110011, funct3=110, and funct7=0000000.

OR Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1

rs2

Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

t1(x6)

0x00000014

t2(x7)

0x00000007

XLEN

31..25

24..20

19..15

14..12

11..7

6..0

0000000

funct7

00111

rs2

00110

rs1

110

funct3

00101

0110011

opcode

Execution Data Path

instruction

0x007362B3

opcode

0110011 -> OP

funct3

110 -> OR bitwise OR

funct7

0000000 -> base ALU op

rd / rs1 / rs2

t0(x5) / t1(x6) / t2(x7)

bitwise ALU

Not computed

t0(x5) = 0x00003001; pc = 0x00002000

Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x007362B3

syntax : or t0(x5), t1(x6), t2(x7)

Pending result: Not computed

Current architectural state

t0(x5) = 0x00003001; pc = 0x00002000

Bit-by-Bit Logic View

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

OR is an RV32I/RV64I base integer R-type logical instruction: it reads two XLEN-wide register values from rs1 and rs2, applies bitwise OR, and writes rd. It is useful for setting target bits selected by a mask or combining bit fields.

opcode=0110011 selects the OP class; funct3=110 with funct7=0000000 selects OR.

OR has no immediate field; use ORI for small immediate set-bit masks and OR for masks or fields already held in registers.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Common Usage Scenarios

Set-bit masks

RV32I/RV64I, x6=20 and x7=7: or x5, x6, x7 gives x5=23 (0x17), setting bits selected by ones in the mask.

Bit-field combination

RV32I/RV64I, x6=20 and x7=7: or x5, x6, x7 gives x5=23 (0x17), setting bits selected by ones in the mask.

Pre-Use Checklist

Syntax Check

rd, rs1 and rs2 select x0–x31 or ABI aliases, with no immediate or rs3.

Semantic Check

OR is an RV32I/RV64I base integer R-type logical instruction: it reads two XLEN-wide register values from rs1 and rs2, applies bitwise OR, and writes rd. It is useful for setting target bits selected by a mask or combining bit fields.
Destination/source overlap uses old source values; x0 is always zero and writes to it are discarded.

Pitfalls / Common Confusions

OR is a bitwise logical operation, not arithmetic addition; it has no immediate field

FAQ

What is the difference between OR and ORI?

OR reads two registers, rs1 and rs2. ORI reads rs1 and uses a sign-extended 12-bit immediate.

Does OR have an immediate operand?

No. OR uses rs1 and rs2 in the R-type encoding; ORI is the bitwise-OR form with a sign-extended 12-bit immediate.