Home/Instructions/AND

AND

RISC-V AND Instruction Details

Instruction ManualR-type

Bitwise AND of rs1 and rs2, result in rd

Instruction Syntax

and rd, rs1, rs2

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

RV32IRV64ILogical

Related Search Terms

AND instruction RISC-V AND and syntax and encoding and R-type and bit mask bitwise AND

Instruction Behavior

AND uses the R-type format. It performs bitwise AND of rs1 and rs2 and writes the result to rd. funct7=0000000 and funct3=111.

AND Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1

rs2

and

Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

t1(x6)

0x00000014

t2(x7)

0x00000007

XLEN

31..25

24..20

19..15

14..12

11..7

6..0

0000000

funct7

00111

rs2

00110

rs1

111

funct3

00101

0110011

opcode

Execution Data Path

instruction

0x007372B3

opcode

0110011 -> OP

funct3

111 -> AND bitwise AND

funct7

0000000 -> base ALU op

rd / rs1 / rs2

t0(x5) / t1(x6) / t2(x7)

bitwise ALU

Not computed

t0(x5) = 0x00003001; pc = 0x00002000

Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x007372B3

syntax : and t0(x5), t1(x6), t2(x7)

Pending result: Not computed

Current architectural state

t0(x5) = 0x00003001; pc = 0x00002000

Bit-by-Bit Logic View

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

AND is an RV32I/RV64I base integer R-type logical instruction: it reads two XLEN-wide register values from rs1 and rs2, applies bitwise AND, and writes rd. It is commonly used to keep bits selected by 1s in a mask and clear bits selected by 0s.

opcode=0110011 selects the OP class; funct3=111 with funct7=0000000 selects AND.

AND has no immediate field. ANDI sign-extends its 12-bit immediate to XLEN; it is not an arbitrary zero-extended 12-bit mask.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120: Official Release

Common Usage Scenarios

Bit Operations & Masks

RV32I/RV64I, x6=20 and x7=7: and x5, x6, x7 gives x5=4; each bit is set only when both input bits are 1.

Pre-Use Checklist

Syntax Check

AND has three GPR fields: rd, rs1 and rs2, with no rs3 or immediate.
opcode=0110011, funct3=111, funct7=0000000.

Semantic Check

Bitwise-AND the two pre-execution XLEN-bit sources; rd=x0 only discards writeback.

Pitfalls / Common Confusions

AND with x0 always yields zero

Alignment mask must be correct

FAQ

What is the difference between AND and ANDI?

AND reads two registers, rs1 and rs2. ANDI reads rs1 and uses a sign-extended 12-bit immediate.

Does AND update condition-code flags?

No. The RISC-V base integer ISA has no condition-code flags; AND only writes rd, and a write to x0 is discarded.