AND
RISC-V AND Instruction Details
Instruction ManualR-typeBitwise AND of rs1 and rs2, result in rd
Instruction Syntax
and rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
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Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
AND uses opcode 0110011 (0x33), funct3 111, funct7 0000000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 111 (0x7)
funct7: 0000000 (0x00)
Instruction Behavior
AND (R-type) performs bitwise AND of rs1 and rs2, writing to rd. funct7=0000000, funct3=111. Used to clear bits (with zero mask), extract bit fields, achieve address alignment (AND with alignment mask), etc.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «and x5, x6, x7 # x5 = x6 & x7».
Bit Operations & Masks
Understand this scenario with real code like «and x5, x6, x7 # x5 = x6 & x7».
Register Operations
Understand this scenario with real code like «and x5, x6, x7 # x5 = x6 & x7».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
AND with x0 always yields zero
Alignment mask must be correct