Is the immediate zero-extended?
ANDI immediate forms use a 12-bit signed immediate that is sign-extended to XLEN.
ANDI
RISC-V ANDI Instruction Details
Instruction ManualI-typeBitwise AND of rs1 with sign-extended 12-bit immediate, result in rd
Instruction Syntax
andi rd, rs1, imm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32ILogical
Instruction Behavior
ANDI performs bitwise AND of rs1 with the sign-extended 12-bit immediate, writing to rd. Used to clear specific bits (masking), extract bit fields, and implement modulo (when immediate is 2^n-1). The immediate is sign-extended first.
ANDI Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
imm
andi
,
,
Execution Context
31..20
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11..7
6..0
000011111111
imm[11:0]
00110
rs1
111
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x0FF37293
opcode
0010011 -> OP-IMM
funct3
111 -> ANDI bitwise AND
rd / rs1
t0(x5) / t1(x6)
imm[11:0]
000011111111 -> sign_extend(255)=0x000000FF
bitwise ALU
0x00000014 & 0x000000FF = 0x00000014
x5
t0(x5) = 0x00000014
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0FF37293
syntax : andi t0(x5), t1(x6), 255
result : t0(x5) = 0x00000014
Bit-by-Bit Logic View
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sign-extended imm
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
ANDI is an RV32I/RV64I OP-IMM logical-immediate instruction: imm[11:0] is sign-extended to XLEN, ANDed bit by bit with rs1, and written to rd. It is useful for masks that fit the signed 12-bit immediate.
opcode=0010011 selects OP-IMM, and funct3=111 selects ANDI.
The I-type imm[11:0] is sign-extended to XLEN; an all-ones encoded immediate represents -1, not zero-extended 4095.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «andi x5, x6, 0xFF # x5 = x6 & 0xFF (extract low byte)».
Bit Operations & Masks
Understand this scenario with real code like «andi x5, x6, 0xFF # x5 = x6 & 0xFF (extract low byte)».
Register Operations
Understand this scenario with real code like «andi x5, x6, 0xFF # x5 = x6 & 0xFF (extract low byte)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Immediate is sign-extended first
ANDI with mask of -1 is effectively a NOP (but HINT if rd=x0)
FAQ
Can andi encode any 32-bit mask?
No. ANDI has only a signed 12-bit immediate field; larger masks usually need to be built in a register and then used with AND.