Is the immediate zero-extended?
XORI immediate forms use a 12-bit signed immediate that is sign-extended to XLEN.
XORI
RISC-V XORI Instruction Details
Instruction ManualI-typeBitwise XOR of rs1 with sign-extended 12-bit immediate, result in rd
Instruction Syntax
xori rd, rs1, imm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32ILogical
Instruction Behavior
XORI performs bitwise XOR of rs1 with the sign-extended 12-bit immediate, writing to rd. XORI rd,rs1,-1 inverts all bits of rs1 (pseudo NOT). Common for bit flipping, data encryption/checksum, register clearing, and complement generation.
XORI Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
imm
xori
,
,
Execution Context
31..20
19..15
14..12
11..7
6..0
111111111111
imm[11:0]
00110
rs1
100
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0xFFF34293
opcode
0010011 -> OP-IMM
funct3
100 -> XORI bitwise XOR
rd / rs1
t0(x5) / t1(x6)
imm[11:0]
111111111111 -> sign_extend(-1)=0xFFFFFFFF
bitwise ALU
0x00000014 ^ 0xFFFFFFFF = 0xFFFFFFEB
x5
t0(x5) = 0xFFFFFFEB
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0xFFF34293
syntax : xori t0(x5), t1(x6), -1
result : t0(x5) = 0xFFFFFFEB
Bit-by-Bit Logic View
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sign-extended imm
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
XORI is an RV32I/RV64I OP-IMM logical-immediate instruction: imm[11:0] is sign-extended to XLEN, XORed bit by bit with rs1, and written to rd. imm=-1 flips every XLEN bit of rs1.
opcode=0010011 selects OP-IMM, and funct3=100 selects XORI.
The I-type imm[11:0] is sign-extended to XLEN; negative immediates extend upper bits with ones.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «xori x5, x6, -1 # x5 = ~x6 (bitwise NOT)».
Crypto & Security
Understand this scenario with real code like «xori x5, x6, -1 # x5 = ~x6 (bitwise NOT)».
Logical Operations
Understand this scenario with real code like «xori x5, x6, -1 # x5 = ~x6 (bitwise NOT)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Immediate range is 12-bit signed; for larger masks, load into a register first
FAQ
Why does xori rd, rs1, -1 invert bits?
-1 is encoded as twelve ones and sign-extends to all ones at XLEN width; XOR with 1 flips each bit.