RVOPcode
Home/Instructions/XOR
XOR

RISC-V XOR Instruction Details

Instruction ManualR-type

Bitwise XOR of rs1 and rs2, result in rd

Instruction Syntax

xor rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32ILogical
Related Search Terms
XOR instructionRISC-V XORxor syntaxxor encodingxor RV32Ibitwise XOR

Instruction Encoding

31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

XOR uses opcode 0110011 (0x33), funct3 100, funct7 0000000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.

Format: R-type
opcode: 0110011 (0x33)
funct3: 100 (0x4)
funct7: 0000000 (0x00)

Instruction Behavior

XOR (R-type) performs bitwise XOR of rs1 and rs2, writing to rd. funct7=0000000, funct3=100. XOR rd,rd,rd is the recommended register clearing method (preferred over ADDI rd,x0,0, no immediate dependency). XOR's self-inverse property (A XOR B XOR B = A) makes it useful for encryption/decryption.

Quick Understanding & Search Notes

XOR is a base integer bitwise logical instruction. It operates across XLEN bits; immediate forms use a sign-extended 12-bit immediate.

The R-type form reads two XLEN-wide operands from rs1 and rs2.
Integer logical operations do not raise arithmetic-overflow exceptions; rd=x0 discards the result.
RISC-V Unprivileged ISA Manual, RV32I

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».

Crypto & Security

Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».

Logical Operations

Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

For register clearing, XOR preferred over ADDI/ADD (no immediate dependency)

FAQ

Is the immediate zero-extended?

XOR immediate forms use a 12-bit signed immediate that is sign-extended to XLEN.

Does it update flags?

The base integer ISA has no condition-code flags; only rd is written.