What is the difference between XOR and XORI?
XOR reads two registers, rs1 and rs2. XORI reads rs1 and uses a sign-extended 12-bit immediate.
XOR
RISC-V XOR Instruction Details
Instruction ManualR-typeBitwise XOR of rs1 and rs2, result in rd
Instruction Syntax
xor rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32ILogical
Instruction Behavior
XOR (R-type) performs bitwise XOR of rs1 and rs2, writing to rd. funct7=0000000, funct3=100. When rs1 and rs2 name the same register, the result is zero; this is a clearing idiom derived from XOR semantics. XOR's self-inverse property (A XOR B XOR B = A) is useful for bit masks and simple reversible transforms.
XOR Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
xor
,
,
Execution Context
31..25
24..20
19..15
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11..7
6..0
0000000
funct7
00111
rs2
00110
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x007342B3
opcode
0110011 -> OP
funct3
100 -> XOR bitwise XOR
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / t2(x7)
immediate
not used
bitwise ALU
0x00000014 ^ 0x00000007 = 0x00000013
x5
t0(x5) = 0x00000013
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x007342B3
syntax : xor t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000013
Bit-by-Bit Logic View
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
XOR is an RV32I/RV64I base integer R-type logical instruction: it reads two XLEN-wide register values from rs1 and rs2, applies bitwise XOR, and writes rd. Each result bit is 1 when the two input bits differ and 0 when they match.
opcode=0110011 selects the OP class; funct3=100 with funct7=0000000 selects XOR.
XOR has no immediate field; use XORI for a 12-bit immediate XOR, noting that XORI sign-extends the immediate first.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».
Crypto & Security
Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».
Logical Operations
Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
For register clearing, XOR preferred over ADDI/ADD (no immediate dependency)
FAQ
Why does xor rd, rs1, rs1 clear a register?
Each bit XORed with itself is 0, so selecting the same register for both sources produces an all-zero XLEN-wide result written to rd.