XOR

RISC-V XOR Instruction Details

Instruction ManualR-type

Bitwise XOR of rs1 and rs2, result in rd

Instruction Syntax

xor rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32ILogical

Instruction Behavior

XOR uses the R-type format. It XORs rs1 and rs2 bit by bit and writes the result to rd. Its encoding is opcode=0110011, funct3=100, funct7=0000000. If both source fields name the same register, every result bit is zero.

XOR Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
rs1
rs2
xor
,
,
Execution Context
t1(x6)
0x00000014
t2(x7)
0x00000007
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00111
rs2
00110
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x007342B3
opcode
0110011 -> OP
funct3
100 -> XOR bitwise XOR
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / t2(x7)
bitwise ALU
0x00000014 ^ 0x00000007 = 0x00000013
x5
t0(x5) = 0x00000013
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x007342B3
syntax : xor t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000013
Architectural Result
t0(x5) = 0x00000013
Bit-by-Bit Logic View
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
rs1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
rs2
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

XOR is an RV32I/RV64I base integer R-type logical instruction: it reads two XLEN-wide register values from rs1 and rs2, applies bitwise XOR, and writes rd. Each result bit is 1 when the two input bits differ and 0 when they match.

opcode=0110011 selects the OP class; funct3=100 with funct7=0000000 selects XOR.
XOR has no immediate field; use XORI for a 12-bit immediate XOR, noting that XORI sign-extends the immediate first.

Common Usage Scenarios

Logical Operations

Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».

Bit Operations & Masks

Understand this scenario with real code like «xor x5, x6, x7 # x5 = x6 ^ x7».

Pre-Use Checklist

Syntax Check
  • Verify rd, rs1, rs2 (and rs3) are valid GPRs.
  • Confirm funct3 and funct7 encoding is correct.
Semantic Check
  • Check if the result affects subsequent branches or address calculations.
  • Ensure the rd register is not overwritten by another instruction.

Pitfalls / Common Confusions

XOR reads two registers; use XORI when one operand must be an immediate.

FAQ

What is the difference between XOR and XORI?

XOR reads two registers, rs1 and rs2. XORI reads rs1 and uses a sign-extended 12-bit immediate.

Why does xor rd, rs1, rs1 clear a register?

Each bit XORed with itself is 0, so selecting the same register for both sources produces an all-zero XLEN-wide result written to rd.