When do SRL and SRA produce different results?
They differ when the top bit of rs1 is 1 and the shift amount is nonzero: SRL fills high bits with zero, while SRA copies the original sign bit.
SRL
RISC-V SRL Instruction Details
Instruction ManualR-typeShift rs1 right logically by the low log2(XLEN) bits of rs2, result in rd
Instruction Syntax
srl rd, rs1, rs2
Operand Breakdown
rd: x0–x31; overlap reads old source values, and x0 writes are discarded.
rs2: the low 5 bits on RV32 or low 6 bits on RV64 supply the shift amount.
Logical right shift zero-fills high bits; rd receives an XLEN-bit result.
RV32IRV64IArithmeticShift
Instruction Behavior
SRL is an R-type logical right shift. It shifts rs1 right by the amount in the low log2(XLEN) bits of rs2: rs2[4:0] on RV32 and rs2[5:0] on RV64. High bits are filled with zero, low bits shifted out are discarded, and rd receives the result. opcode=0110011, funct3=101, funct7=0000000; with the same funct3, funct7=0100000 selects SRA.
SRL Decode And Execute Animation
RV32I/RV64I; XLEN-bit logical right shift
srl rd, rs1, rs2Execution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
This example fixes IALIGN=32 and a 32-bit instruction; PC must be 4-byte aligned.
32-bit encoding
0x00C5D533funct7 [31..25]
0000000
rs2 [24..20]
01100 → x12
rs1 [19..15]
01011 → x11
funct3 [14..12]
101
rd [11..7]
01010 → x10
opcode [6..0]
0110011
x11=0x00000014; x12=0x00000002
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x00000007; PC=0x00002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
SRL takes a variable shift amount from the low bits of rs2, logically shifts rs1 right, and fills high bits with zero. It fits unsigned values or bit-field extraction and does not preserve sign.
opcode=0110011, funct3=101, and funct7=0000000 select SRL.
SRL and SRA share funct3=101; funct7/bit30 distinguishes logical from arithmetic right shift.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srl x5, x6, x7 # x5 = x6 >> (x7[4:0] on RV32, x7[5:0] on RV64) (logical)».
Pre-Use Checklist
Syntax Check
- rd, rs1 and optional rs2 select x0–x31 or ABI names; there is no rs3.
- The shift amount uses rs2[4:0] on RV32 or rs2[5:0] on RV64.
Semantic Check
- Shift rs1 right logically by the low log2(XLEN) bits of rs2, result in rd
- Overlapping registers read sources before writeback; rd=x0 is a HINT, with only PC and applicable performance-counter advancement, and implementations may ignore it.
Pitfalls / Common Confusions
SRL fills high bits with zero; do not use it as a sign-preserving right shift.
The shift amount uses only the low log2(XLEN) bits of rs2, with different effective widths on RV32 and RV64.
rd=x0 is a HINT designated for future standard use; it does not change architecturally visible state except PC and applicable performance counters, and an implementation may ignore it.
FAQ
Is SRL the same as unsigned division by a power of two?
Under an unsigned binary interpretation, logical right shift is commonly used for division by powers of two. The animation shows only the ISA-defined bit shift result, not language-level overflow or rounding rules.