When do SRL and SRA produce different results?
They differ when the top bit of rs1 is 1 and the shift amount is nonzero: SRL fills high bits with zero, while SRA copies the original sign bit.
SRL
RISC-V SRL Instruction Details
Instruction ManualR-typeShift rs1 right logically by the low log2(XLEN) bits of rs2, result in rd
Instruction Syntax
srl rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32IRV64IArithmeticShift
Instruction Behavior
SRL is an R-type logical right shift. It shifts rs1 right by the amount in the low log2(XLEN) bits of rs2: rs2[4:0] on RV32 and rs2[5:0] on RV64. High bits are filled with zero, low bits shifted out are discarded, and rd receives the result. opcode=0110011, funct3=101, funct7=0000000; with the same funct3, funct7=0100000 selects SRA.
SRL Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
srl
,
,
Execution Context
t1(x6)
0x00000014
sp(x2)
0x00000002
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00010
rs2
00110
rs1
101
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x002352B3
opcode
0110011 -> OP
funct3
101 -> SRL
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / sp(x2)
shamt
rs2 low 5 bits -> 2
ALU
0x00000014 >> 2 = 0x00000005
x5
t0(x5) = 0x00000005
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x002352B3
syntax : srl t0(x5), t1(x6), sp(x2)
result : t0(x5) = 0x00000005
Architectural Result
t0(x5) = 0x00000005
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRL takes a variable shift amount from the low bits of rs2, logically shifts rs1 right, and fills high bits with zero. It fits unsigned values or bit-field extraction and does not preserve sign.
opcode=0110011, funct3=101, and funct7=0000000 select SRL.
SRL and SRA share funct3=101; funct7/bit30 distinguishes logical from arithmetic right shift.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srl x5, x6, x7 # x5 = x6 >> (x7[4:0] on RV32, x7[5:0] on RV64) (logical)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
SRL fills high bits with zero; do not use it as a sign-preserving right shift.
The shift amount uses only the low log2(XLEN) bits of rs2, with different effective widths on RV32 and RV64.
rd=x0 is a HINT designated for future standard use; it does not change architecturally visible state except PC and applicable performance counters, and an implementation may ignore it.
FAQ
Is SRL the same as unsigned division by a power of two?
Under an unsigned binary interpretation, logical right shift is commonly used for division by powers of two. The animation shows only the ISA-defined bit shift result, not language-level overflow or rounding rules.