Do SRLI and SRAI differ by only one bit?
In base shift-immediate encoding, they share opcode and funct3; bit30 in the fixed high bits selects SRLI when 0 and SRAI when 1.
SRLI
RISC-V SRLI Instruction Details
Instruction ManualI-typeShift rs1 right logically by shamt bits (zeros into MSBs), result in rd
Instruction Syntax
srli rd, rs1, shamt
Operand Breakdown
rd: x0–x31; overlap reads old source values, and x0 writes are discarded.
shamt: 0–31 on RV32 or 0–63 on RV64; the remaining high immediate bits are fixed to zero.
Logical right shift zero-fills high bits; rd receives an XLEN-bit result.
RV32IRV64IArithmeticShift
Instruction Behavior
SRLI is the I-type immediate logical right-shift form. It shifts rs1 right by shamt, fills high bits with zero, discards low bits shifted out, and writes rd. RV32 uses imm[4:0] as shamt, range 0..31; RV64 uses a 6-bit shamt with bit25 as shamt[5]. opcode=0010011, funct3=101; fixed high bits/bit30=0 distinguish SRLI from SRAI.
SRLI Decode And Execute Animation
RV32I/RV64I; XLEN-bit logical right shift
srli rd, rs1, shamtExecution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
This example fixes IALIGN=32 and a 32-bit instruction; PC must be 4-byte aligned.
32-bit encoding
0x0025D513fixed imm[11:5] [31..25]
0000000
shamt[4:0] [24..20]
00010
rs1 [19..15]
01011 → x11
funct3 [14..12]
101
rd [11..7]
01010 → x10
opcode [6..0]
0010011
x11=0x00000014; shamt=2
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x00000007; PC=0x00002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
SRLI logically shifts rs1 right by the shamt constant and fills high bits with zero. It is commonly used for unsigned right shifts, field extraction, or scaling after dropping low bits.
opcode=0010011 with funct3=101 selects a right shift-immediate class; fixed high bits/bit30 choose SRLI or SRAI.
RV32 and RV64 have different shamt widths; out-of-range inputs are not used by the animation encoding or calculation.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srli x5, x6, 8 # RV32I/RV64I: x6=0x1234 -> x5=0x12 (logical right shift)».
Pre-Use Checklist
Syntax Check
- rd, rs1 and optional rs2 select x0–x31 or ABI names; there is no rs3.
- shamt is 0–31 on RV32 or 0–63 on RV64; other high immediate bits are fixed to zero.
Semantic Check
- Shift rs1 right logically by shamt bits (zeros into MSBs), result in rd
- Overlapping registers read sources before writeback; rd=x0 is a HINT, with only PC and applicable performance-counter advancement, and implementations may ignore it.
Pitfalls / Common Confusions
SRLI always fills high bits with zero; use SRAI when sign preservation is needed.
shamt is a shift-immediate field: 0..31 on RV32 and 0..63 on RV64.
rd=x0 is a custom HINT; it does not change architecturally visible state except PC and applicable performance counters, and an implementation may ignore it.
FAQ
Can SRLI use a negative shamt?
No. shamt is a nonnegative shift amount: 0..31 on RV32 and 0..63 on RV64.