Do SRLI and SRAI differ by only one bit?
In base shift-immediate encoding, they share opcode and funct3; bit30 in the fixed high bits selects SRLI when 0 and SRAI when 1.
SRLI
RISC-V SRLI Instruction Details
Instruction ManualI-typeShift rs1 right logically by shamt bits (zeros into MSBs), result in rd
Instruction Syntax
srli rd, rs1, shamt
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IArithmeticShift
Instruction Behavior
SRLI is the I-type immediate logical right-shift form. It shifts rs1 right by shamt, fills high bits with zero, discards low bits shifted out, and writes rd. RV32 uses imm[4:0] as shamt, range 0..31; RV64 uses a 6-bit shamt with bit25 as shamt[5]. opcode=0010011, funct3=101; fixed high bits/bit30=0 distinguish SRLI from SRAI.
SRLI Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
srli
,
,
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0000000
fixed imm[11:5]
00010
shamt[4:0]
00110
rs1
101
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x00235293
opcode
0010011 -> OP-IMM
funct3
101 -> SRLI
imm[11:5]
imm[11:5]=0000000 fixed
rd / rs1
t0(x5) / t1(x6)
imm[11:5] + shamt[4:0]
imm[11:5]=0000000 fixed; shamt[4:0]=00010
shift
0x00000014 >> 2 = 0x00000005
x5
t0(x5) = 0x00000005
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00235293
syntax : srli t0(x5), t1(x6), 2
result : t0(x5) = 0x00000005
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRLI logically shifts rs1 right by the shamt constant and fills high bits with zero. It is commonly used for unsigned right shifts, field extraction, or scaling after dropping low bits.
opcode=0010011 with funct3=101 selects a right shift-immediate class; fixed high bits/bit30 choose SRLI or SRAI.
RV32 and RV64 have different shamt widths; out-of-range inputs are not used by the animation encoding or calculation.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srli x5, x6, 2 # x5 = x6 >> 2 (unsigned divide by 4)».
Multiplication & Division
Understand this scenario with real code like «srli x5, x6, 2 # x5 = x6 >> 2 (unsigned divide by 4)».
Type Conversion
Understand this scenario with real code like «srli x5, x6, 2 # x5 = x6 >> 2 (unsigned divide by 4)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
SRLI always fills high bits with zero; use SRAI when sign preservation is needed.
shamt is a shift-immediate field: 0..31 on RV32 and 0..63 on RV64.
FAQ
Can SRLI use a negative shamt?
No. shamt is a nonnegative shift amount: 0..31 on RV32 and 0..63 on RV64.