What immediate range can SLLI encode?
As a shift amount, RV32 encodes 0..31 and RV64 encodes 0..63. It is not the ordinary -2048..2047 I-type arithmetic immediate.
SLLI
RISC-V SLLI Instruction Details
Instruction ManualI-typeShift rs1 left logically by shamt bits (zeros into LSBs), result in rd
Instruction Syntax
slli rd, rs1, shamt
Operand Breakdown
rd: selects x0–x31; writes to x0 are discarded. rs1: supplies the source value before writeback.
shamt: 0–31 on RV32 or 0–63 on RV64; remaining high immediate bits are fixed to zero, not a signed 12-bit operand.
Logical left shift fills low bits with zero and discards high bits beyond XLEN.
RV32IRV64IArithmeticShift
Instruction Behavior
SLLI is the I-type immediate logical left-shift form. It shifts rs1 left by shamt, fills low bits with zero, discards overflowed high bits, and writes the XLEN-truncated result to rd. RV32 uses imm[4:0] as shamt, range 0..31; RV64 uses a 6-bit shamt with imm[5] in bit25, while the remaining high bits are fixed for legal shift-immediate encodings. opcode=0010011, funct3=001.
SLLI Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
slli
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0000000
fixed imm[11:5]
00010
shamt[4:0]
00110
rs1
001
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x00231293
opcode
0010011 -> OP-IMM
funct3
001 -> SLLI
imm[11:5]
imm[11:5]=0000000 fixed
rd / rs1
t0(x5) / t1(x6)
imm[11:5] + shamt[4:0]
imm[11:5]=0000000 fixed; shamt[4:0]=00010
shift
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00231293
syntax : slli t0(x5), t1(x6), 2
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLLI shifts rs1 left by the shamt constant in the syntax. It uses specialized shift-immediate encoding, not a normal signed imm[11:0] operand.
opcode=0010011 selects OP-IMM, and funct3=001 selects the left shift-immediate form.
RV32 has a 5-bit shamt; RV64 has a 6-bit shamt, so changing XLEN in the animation changes the valid range and bit25 meaning.
Common Usage Scenarios
Bit operations and shifts
RV32I/RV64I, x6=20: slli x5, x6, 2 gives x5=80 (0x50); shamt is an encodable constant.
Pre-Use Checklist
Syntax Check
- Register operands select x0–x31 or their ABI names; sources use values before writeback.
- SLLI shamt is 0–31 on RV32 or 0–63 on RV64; remaining high immediate bits are fixed to zero, and shamt is not sign-extended.
Semantic Check
- Shift rs1 left logically by shamt bits (zeros into LSBs), result in rd
- x0 is always zero and discards writes; integer computation raises no arithmetic exception.
Pitfalls / Common Confusions
shamt must be a nonnegative encodable shift amount: 0..31 on RV32 and 0..63 on RV64.
SLLI is not an ordinary signed 12-bit immediate operation; high immediate bits are fixed encoding bits and, on RV64, part of the shift amount.
FAQ
Does SLLI keep bits shifted out on the left?
No. High bits shifted beyond XLEN are discarded, low bits are filled with zero, and rd receives only the XLEN-bit result.