Why is the SLL shift amount not all of rs2?
The base integer semantics define register shifts to use only the low log2(XLEN) bits of rs2, so RV32 uses 5 bits and RV64 uses 6 bits.
SLL
RISC-V SLL Instruction Details
Instruction ManualR-typeShift rs1 left logically by the low log2(XLEN) bits of rs2, result in rd
Instruction Syntax
sll rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32IArithmeticShift
Instruction Behavior
SLL is an R-type logical left shift. It shifts rs1 left by the amount in the low log2(XLEN) bits of rs2: rs2[4:0] on RV32 and rs2[5:0] on RV64. High bits shifted out are discarded, low bits are filled with zero, and the XLEN-truncated result is written to rd. opcode=0110011, funct3=001, funct7=0000000.
SLL Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sll
,
,
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00010
rs2
00110
rs1
001
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x002312B3
opcode
0110011 -> OP
funct3
001 -> SLL
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / sp(x2)
shamt
rs2 low 5 bits -> 2
ALU
0x00000014 << 2 = 0x00000050
x5
t0(x5) = 0x00000050
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x002312B3
syntax : sll t0(x5), t1(x6), sp(x2)
result : t0(x5) = 0x00000050
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLL takes a variable shift amount from the low log2(XLEN) bits of rs2, logically shifts rs1 left, fills low bits with zero, discards overflowed high bits, and writes rd.
opcode=0110011 selects the OP class; funct3=001 with funct7=0000000 selects SLL.
The register shift amount depends on XLEN: RV32 uses the low 5 bits, and RV64 uses the low 6 bits.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «sll x5, x6, x7 # x5 = x6 << (x7[4:0] on RV32, x7[5:0] on RV64)».
Multiplication & Division
Understand this scenario with real code like «sll x5, x6, x7 # x5 = x6 << (x7[4:0] on RV32, x7[5:0] on RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The shift amount uses only the low log2(XLEN) bits of rs2; the other high bits of rs2 do not contribute to the amount.
SLL is a logical left shift: low bits are filled with zero, high bits shifted out are discarded, and no exception or flag is produced.
FAQ
When should I use SLL instead of SLLI?
Use SLL when the shift amount is a run-time register value. Use SLLI when the amount is an encodable constant.