Why is the SLL shift amount not all of rs2?
The base integer semantics define register shifts to use only the low log2(XLEN) bits of rs2, so RV32 uses 5 bits and RV64 uses 6 bits.
SLL
RISC-V SLL Instruction Details
Instruction ManualR-typeShift rs1 left logically by the low log2(XLEN) bits of rs2, result in rd
Instruction Syntax
sll rd, rs1, rs2
Operand Breakdown
rd: selects x0–x31; writes to x0 are discarded. rs1: supplies the source value before writeback.
rs2: only its low 5 bits on RV32 or low 6 bits on RV64 supply the shift amount.
Logical left shift fills low bits with zero and discards high bits beyond XLEN.
RV32IRV64IArithmeticShift
Instruction Behavior
SLL is an R-type logical left shift. It shifts rs1 left by the amount in the low log2(XLEN) bits of rs2: rs2[4:0] on RV32 and rs2[5:0] on RV64. High bits shifted out are discarded, low bits are filled with zero, and the XLEN-truncated result is written to rd. opcode=0110011, funct3=001, funct7=0000000.
SLL Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sll
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x00000014
sp(x2)
0x00000002
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00010
rs2
00110
rs1
001
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x002312B3
opcode
0110011 -> OP
funct3
001 -> SLL
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / sp(x2)
shamt
rs2 low 5 bits -> 2
ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x002312B3
syntax : sll t0(x5), t1(x6), sp(x2)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLL takes a variable shift amount from the low log2(XLEN) bits of rs2, logically shifts rs1 left, fills low bits with zero, discards overflowed high bits, and writes rd.
opcode=0110011 selects the OP class; funct3=001 with funct7=0000000 selects SLL.
The register shift amount depends on XLEN: RV32 uses the low 5 bits, and RV64 uses the low 6 bits.
Common Usage Scenarios
Bit operations and shifts
RV32I/RV64I, x6=20 and x7=2: sll x5, x6, x7 gives x5=80 (0x50), retaining only low XLEN bits.
Pre-Use Checklist
Syntax Check
- Register operands select x0–x31 or their ABI names; sources use values before writeback.
- rd, rs1 and rs2 are register fields with no immediate operand.
Semantic Check
- Shift rs1 left logically by the low log2(XLEN) bits of rs2, result in rd
- x0 is always zero and discards writes; integer computation raises no arithmetic exception.
Pitfalls / Common Confusions
The shift amount uses only the low log2(XLEN) bits of rs2; the other high bits of rs2 do not contribute to the amount.
SLL is a logical left shift: low bits are filled with zero, high bits shifted out are discarded, and no arithmetic exception or flag is produced.
FAQ
When should I use SLL instead of SLLI?
Use SLL when the shift amount is a run-time register value. Use SLLI when the amount is an encodable constant.