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SLL

RISC-V SLL Instruction Details

Instruction ManualR-type

Shift rs1 left logically by the low log2(XLEN) bits of rs2, result in rd

Instruction Syntax

sll rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32IArithmeticShift
Related Search Terms
SLL instructionRISC-V SLLsll syntaxsll encodingsll R-typeSLL vs SLLIsll shift

Instruction Encoding

31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

SLL uses opcode 0110011 (0x33), funct3 001, funct7 0000000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.

Format: R-type
opcode: 0110011 (0x33)
funct3: 001 (0x1)
funct7: 0000000 (0x00)

Instruction Behavior

SLL shifts rs1 left logically by the amount in the low log2(XLEN) bits of rs2 (rs2[4:0] on RV32, rs2[5:0] on RV64), filling LSBs with zeros. Result in rd. funct7=0000000, funct3=001. Unlike SLLI (immediate shift), SLL allows a variable shift amount from a register.

Quick Understanding & Search Notes

SLL performs a logical left shift, fills low bits with zeros, and writes rd. The shift amount comes from the low log2(XLEN) bits of rs2.

Register shifts use only the low log2(XLEN) bits of rs2 as the shift amount.
Logical right shift fills with zeros; arithmetic right shift copies the sign bit, matching different signed/unsigned use cases.
RISC-V Unprivileged ISA Manual: RV32I Base Integer Instruction Set

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «sll x5, x6, x7 # x5 = x6 << (x7[4:0])».

Multiplication & Division

Understand this scenario with real code like «sll x5, x6, x7 # x5 = x6 << (x7[4:0])».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Shift amount uses the low log2(XLEN) bits of rs2: low 5 bits on RV32, low 6 bits on RV64
rs2[4:0]=0 yields rs1 unchanged

FAQ

Where does the SLL shift amount come from?

For register shifts, the amount comes from the low log2(XLEN) bits of rs2.

What is the difference between logical and arithmetic right shift?

Logical right shift fills high bits with zeros. Arithmetic right shift copies the original sign bit, which is usually used to preserve signedness.