What encoding field distinguishes SRA from SRL?
They share opcode=0110011 and funct3=101; SRA uses funct7=0100000, while SRL uses funct7=0000000.
SRA
RISC-V SRA Instruction Details
Instruction ManualR-typeShift rs1 right arithmetically by the low log2(XLEN) bits of rs2, result in rd
Instruction Syntax
sra rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV32IRV64IArithmeticShift
Instruction Behavior
SRA is an R-type arithmetic right shift. It shifts rs1 right by the amount in the low log2(XLEN) bits of rs2: rs2[4:0] on RV32 and rs2[5:0] on RV64. High bits are filled with the original most-significant bit of rs1, low bits shifted out are discarded, and rd receives the result. opcode=0110011, funct3=101, funct7=0100000; with the same funct3, funct7=0000000 selects SRL.
SRA Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sra
,
,
Execution Context
a6(x16)
0xFFFFFFF0
sp(x2)
0x00000002
31..25
24..20
19..15
14..12
11..7
6..0
0100000
funct7
00010
rs2
10000
rs1
101
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x402852B3
opcode
0110011 -> OP
funct3
101 -> SRA
funct7
0100000 -> base ALU selector
rd / rs1 / rs2
t0(x5) / a6(x16) / sp(x2)
shamt
rs2 low 5 bits -> 2
ALU
0xFFFFFFF0 arithmetic >> 2 = 0xFFFFFFFC
x5
t0(x5) = 0xFFFFFFFC
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x402852B3
syntax : sra t0(x5), a6(x16), sp(x2)
result : t0(x5) = 0xFFFFFFFC
Architectural Result
t0(x5) = 0xFFFFFFFC
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRA takes a variable shift amount from the low bits of rs2, arithmetically shifts rs1 right, and fills new high bits with the original most-significant bit. It preserves two's-complement sign shape, but is not identical to signed division in every language context.
opcode=0110011, funct3=101, and funct7=0100000 select SRA.
The register shift amount still uses only the low log2(XLEN) bits of rs2; the arithmetic behavior comes from filling high bits with the original most-significant bit.
Common Usage Scenarios
Bit Operations
Understand this scenario with real code like «sra x5, x6, x7 # x5 = x6 >> (x7[4:0] on RV32, x7[5:0] on RV64) (arithmetic)».
Type Conversion
Understand this scenario with real code like «sra x5, x6, x7 # x5 = x6 >> (x7[4:0] on RV32, x7[5:0] on RV64) (arithmetic)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
SRA copies the original most-significant bit of rs1; it is not the same as zero-filling SRL.
Arithmetic right shift of negative values is not identical to integer division rounded toward zero; do not treat it as an unconditional signed divide.
With rd=x0, SRA is a HINT designated for future standard use and does not perform the normal destination-register update.
FAQ
Can SRA directly replace signed division?
Not unconditionally. For negative values, arithmetic right shift copies the sign bit and typically rounds toward negative infinity, while integer division in many software semantics truncates toward zero.