What encoding field distinguishes SRA from SRL?
They share opcode=0110011 and funct3=101; SRA uses funct7=0100000, while SRL uses funct7=0000000.
SRA
RISC-V SRA Instruction Details
Instruction ManualR-typeShift rs1 right arithmetically by the low log2(XLEN) bits of rs2, result in rd
Instruction Syntax
sra rd, rs1, rs2
Operand Breakdown
rd: selects x0–x31; overlap uses source values before writeback, and x0 writes are discarded.
rs2: only its low 5 bits on RV32 or low 6 bits on RV64 supply the shift amount.
Arithmetic right shift copies the original rs1 sign bit: bit31 on RV32, bit63 on RV64.
RV32IRV64IArithmeticShift
Instruction Behavior
SRA is an R-type arithmetic right shift. It shifts rs1 right by the amount in the low log2(XLEN) bits of rs2: rs2[4:0] on RV32 and rs2[5:0] on RV64. High bits are filled with the original most-significant bit of rs1, low bits shifted out are discarded, and rd receives the result. opcode=0110011, funct3=101, funct7=0100000; with the same funct3, funct7=0000000 selects SRL.
SRA Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sra
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
a6(x16)
0xFFFFFFF0
sp(x2)
0x00000002
31..25
24..20
19..15
14..12
11..7
6..0
0100000
funct7
00010
rs2
10000
rs1
101
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x402852B3
opcode
0110011 -> OP
funct3
101 -> SRA
funct7
0100000 -> base ALU selector
rd / rs1 / rs2
t0(x5) / a6(x16) / sp(x2)
shamt
rs2 low 5 bits -> 2
ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x402852B3
syntax : sra t0(x5), a6(x16), sp(x2)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRA shifts rs1 right arithmetically, filling high bits with its original sign bit. Negative results round down, unlike DIV rounding toward zero.
opcode=0110011, funct3=101, and funct7=0100000 select SRA.
The register shift amount still uses only the low log2(XLEN) bits of rs2; the arithmetic behavior comes from filling high bits with the original most-significant bit.
Common Usage Scenarios
Bit Operations
Understand this scenario with real code like «sra x5, x6, x7 # x5 = x6 >> (x7[4:0] on RV32, x7[5:0] on RV64) (arithmetic)».
Type Conversion
Understand this scenario with real code like «sra x5, x6, x7 # x5 = x6 >> (x7[4:0] on RV32, x7[5:0] on RV64) (arithmetic)».
Pre-Use Checklist
Syntax Check
- Registers select x0–x31; overlapping operands read values before writeback.
- This R-type form has no immediate; SRA uses only the effective low rs2 bits.
Semantic Check
- Use the instruction's signed/unsigned comparison interpretation or arithmetic sign-fill rule.
- rd=x0 is a HINT with unchanged general registers; SRAI x0,x0,7 is the semihosting exit marker.
Pitfalls / Common Confusions
SRA copies the original most-significant bit of rs1; it is not the same as zero-filling SRL.
For example, -3 shifted right arithmetically by 1 gives -2, while DIV of -3 by 2 gives -1; the operations are not interchangeable.
With rd=x0, SRA is a HINT designated for future standard use and does not perform the normal destination-register update.
FAQ
Can SRA directly replace signed division?
Not unconditionally. Sign-filling arithmetic right shift gives -2 for -3 shifted by 1; RISC-V DIV rounds -3 / 2 toward zero to -1.