Which bit does SRAI copy on RV64?
SRAI copies the original most-significant bit of rs1: bit31 on RV32 and bit63 on RV64.
SRAI
RISC-V SRAI Instruction Details
Instruction ManualI-typeShift rs1 right arithmetically by shamt bits (sign-bit into MSBs), result in rd
Instruction Syntax
srai rd, rs1, shamt
Operand Breakdown
rd: selects x0–x31; overlap uses source values before writeback, and x0 writes are discarded.
shamt: 0–31 on RV32, 0–63 on RV64; not a signed 12-bit immediate.
Arithmetic right shift copies the original rs1 sign bit: bit31 on RV32, bit63 on RV64.
RV32IRV64IArithmeticShift
Instruction Behavior
SRAI is the I-type immediate arithmetic right-shift form. It shifts rs1 right by shamt, fills high bits with the original most-significant bit of rs1, discards low bits shifted out, and writes rd. RV32 uses imm[4:0] as shamt, range 0..31; RV64 uses a 6-bit shamt with bit25 as shamt[5]. opcode=0010011, funct3=101; fixed high bits/bit30=1 distinguish SRAI from SRLI.
SRAI Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
srai
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
a6(x16)
0xFFFFFFF0
31..25
24..20
19..15
14..12
11..7
6..0
0100000
fixed imm[11:5]
00010
shamt[4:0]
10000
rs1
101
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x40285293
opcode
0010011 -> OP-IMM
funct3
101 -> SRAI
imm[11:5]
imm[11:5]=0100000 fixed
rd / rs1
t0(x5) / a6(x16)
imm[11:5] + shamt[4:0]
imm[11:5]=0100000 fixed; shamt[4:0]=00010
shift
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x40285293
syntax : srai t0(x5), a6(x16), 2
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRAI shifts rs1 right arithmetically, filling high bits with its original sign bit. Negative results round down, unlike DIV rounding toward zero.
opcode=0010011 with funct3=101 selects a right shift-immediate class; fixed high bits/bit30=1 selects SRAI.
The sign bit used by SRAI depends on XLEN: bit31 on RV32 and bit63 on RV64.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srai x5, x6, 2 # x5 = x6 >> 2 (signed, sign-extended)».
Type Conversion
Understand this scenario with real code like «srai x5, x6, 2 # x5 = x6 >> 2 (signed, sign-extended)».
Pre-Use Checklist
Syntax Check
- Registers select x0–x31; overlapping operands read values before writeback.
- shamt is 0–31 on RV32 or 0–63 on RV64; do not sign-extend it as a 12-bit operand.
Semantic Check
- Use the instruction's signed/unsigned comparison interpretation or arithmetic sign-fill rule.
- rd=x0 is a HINT with unchanged general registers; SRAI x0,x0,7 is the semihosting exit marker.
Pitfalls / Common Confusions
SRAI fills high bits from the original most-significant bit of rs1; on RV64 this is bit63, not always bit31.
shamt is a nonnegative shift amount: 0..31 on RV32 and 0..63 on RV64.
For example, -3 shifted right arithmetically by 1 gives -2, while DIV of -3 by 2 gives -1; the operations are not interchangeable.
rd=x0, rs1=x0, shamt=7 is the standard semihosting exit marker; other SRAI rd=x0 HINT encodings do not perform the normal destination-register update.
FAQ
Do SRAI and SRLI have the same shamt range?
For the same XLEN, yes: 0..31 on RV32 and 0..63 on RV64. The fixed high bits/bit30 choose arithmetic sign-fill versus logical zero-fill.