Which bit does SRAI copy on RV64?
SRAI copies the original most-significant bit of rs1: bit31 on RV32 and bit63 on RV64.
SRAI
RISC-V SRAI Instruction Details
Instruction ManualI-typeShift rs1 right arithmetically by shamt bits (sign-bit into MSBs), result in rd
Instruction Syntax
srai rd, rs1, shamt
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IArithmeticShift
Instruction Behavior
SRAI is the I-type immediate arithmetic right-shift form. It shifts rs1 right by shamt, fills high bits with the original most-significant bit of rs1, discards low bits shifted out, and writes rd. RV32 uses imm[4:0] as shamt, range 0..31; RV64 uses a 6-bit shamt with bit25 as shamt[5]. opcode=0010011, funct3=101; fixed high bits/bit30=1 distinguish SRAI from SRLI.
SRAI Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
srai
,
,
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0100000
fixed imm[11:5]
00010
shamt[4:0]
10000
rs1
101
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x40285293
opcode
0010011 -> OP-IMM
funct3
101 -> SRAI
imm[11:5]
imm[11:5]=0100000 fixed
rd / rs1
t0(x5) / a6(x16)
imm[11:5] + shamt[4:0]
imm[11:5]=0100000 fixed; shamt[4:0]=00010
shift
0xFFFFFFF0 arithmetic >> 2 = 0xFFFFFFFC
x5
t0(x5) = 0xFFFFFFFC
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x40285293
syntax : srai t0(x5), a6(x16), 2
result : t0(x5) = 0xFFFFFFFC
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRAI arithmetically shifts rs1 right by the shamt constant and fills new high bits with the original most-significant bit. It is a sign-preserving right shift, but negative results should not be simplified to truncating division toward zero.
opcode=0010011 with funct3=101 selects a right shift-immediate class; fixed high bits/bit30=1 selects SRAI.
The sign bit used by SRAI depends on XLEN: bit31 on RV32 and bit63 on RV64.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srai x5, x6, 2 # x5 = x6 >> 2 (signed, sign-extended)».
Multiplication & Division
Understand this scenario with real code like «srai x5, x6, 2 # x5 = x6 >> 2 (signed, sign-extended)».
Type Conversion
Understand this scenario with real code like «srai x5, x6, 2 # x5 = x6 >> 2 (signed, sign-extended)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
SRAI fills high bits from the original most-significant bit of rs1; on RV64 this is bit63, not always bit31.
shamt is a nonnegative shift amount: 0..31 on RV32 and 0..63 on RV64.
Arithmetic right shift of negative values is not the same as truncating division by a power of two in every context.
FAQ
Do SRAI and SRLI have the same shamt range?
For the same XLEN, yes: 0..31 on RV32 and 0..63 on RV64. The fixed high bits/bit30 choose arithmetic sign-fill versus logical zero-fill.