What value does SLTI write?
It writes 1 when the comparison is true, otherwise 0.
SLTI
RISC-V SLTI Instruction Details
Instruction ManualI-typeCompare rs1 with a sign-extended 12-bit immediate as signed values; write 1 if less, otherwise 0
Instruction Syntax
slti rd, rs1, imm
Operand Breakdown
rd: selects x0–x31; overlap uses source values before writeback, and x0 writes are discarded.
imm: -2048 through 2047, sign-extended to XLEN before signed comparison.
rd is 1 if less, otherwise 0; this is not a conditional branch.
RV32IRV64IArithmeticCompare
Instruction Behavior
SLTI (signed) compares rs1 with the sign-extended 12-bit immediate, setting rd to 1 if rs1 < imm (signed), else 0. Used for single-step comparison and range checking in loops.
SLTI Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
imm
slti
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
a6(x16)
0xFFFFFFF0
31..20
19..15
14..12
11..7
6..0
000000001010
imm[11:0]
10000
rs1
010
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x00A82293
opcode
0010011 -> OP-IMM
funct3
010 -> SLTI
rd / rs1
t0(x5) / a6(x16)
imm[11:0]
imm[11:0]=000000001010 -> sign_extend=0x0000000A (signed)
compare
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00A82293
syntax : slti t0(x5), a6(x16), 10
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLTI performs signed comparison rs1 < imm; rd is set to 1 when true and 0 otherwise. It turns a comparison result into an integer value usable by later arithmetic or branches.
The immediate form uses a sign-extended 12-bit immediate.
Signed and unsigned comparisons differ in how the bit patterns are interpreted, not in register width.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «slti x5, x6, 10 # x5 = (x6 < 10) ? 1 : 0 (signed)».
Pre-Use Checklist
Syntax Check
- Registers select x0–x31; overlapping operands read values before writeback.
- The 12-bit immediate is -2048..2047 and is sign-extended to XLEN before comparison.
Semantic Check
- Use the instruction's signed/unsigned comparison interpretation or arithmetic sign-fill rule.
- rd=x0 is a HINT with unchanged general registers; SRAI x0,x0,7 is the semihosting exit marker.
Pitfalls / Common Confusions
Result is boolean (0 or 1), not difference sign
Immediate is sign-extended before comparison
With rd=x0, SLTI is a custom HINT: general registers remain unchanged and the PC advances normally.
FAQ
What is the difference between SLT and SLTU?
SLT/SLTI compare as signed integers; SLTU/SLTIU compare as unsigned integers.