Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
DRET
RISC-V DRET Instruction Details
Instruction ManualI-typeDebug mode return: PC<-dpc, restore privilege. Only in D-mode.
Instruction Syntax
dret
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
DebugSystem & Privileged
Instruction Behavior
DRET returns from Debug Mode (D-mode) to normal execution. Operation: 1) PC←dpc (debug program counter); 2) restore privilege mode from before debug entry. Only legal in D-mode. DRET has no interrupt-enable restoration — debug mode does not manage interrupts via mstatus.
Quick Understanding & Search Notes
DRET is a system-level instruction defined by the debug specification. This page covers architectural semantics only, not platform firmware policy.
Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
Executing at an unsupported privilege level or without the required extension raises the specified exception.
Common Usage Scenarios
Debugger return
Understand this scenario with real code like «dret».
Hardware breakpoint resume
Understand this scenario with real code like «dret».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only in Debug Mode
Not standard ISA
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.