Is SD available only on RV64?
RV64I defines single-register SD. RV32 Zilsd also defines SD with the same encoding but an even/odd source register pair; the animation demonstrates RV64I only.
SD
RISC-V SD Instruction Details
Instruction ManualS-typeRV64I: store the 64-bit value in rs2; RV32 Zilsd: store a 64-bit value from an even/odd register pair.
Instruction Syntax
sd rs2, offset(rs1)
Operand Breakdown
rs2: RV64I stores one 64-bit register; RV32 Zilsd requires even rs2, with low/high 32 bits from rs2/rs2+1.
Odd rs2 encodings are reserved in Zilsd; rs2=x0 supplies an entirely zero 64-bit source without reading x1.
rs1 is the base; offset is a sign-extended 12-bit byte displacement from -2048 through 2047; SD writes no GPR.
RV64IZilsdMemory Store
Extension condition: RV64I uses one 64-bit rs2; RV32 requires Zilsd, with an even rs2 selecting a register pair.
Related Search Terms
Instruction Behavior
SD uses a 32-bit S-type encoding (opcode=0100011, funct3=011). RV64I stores the 64-bit rs2 value at rs1 plus a sign-extended 12-bit offset; address calculation wraps to XLEN. RV32 Zilsd reuses this encoding and requires even rs2: rs2 holds the low 32 bits and rs2+1 the high 32 bits, regardless of endianness. With rs2=x0 the entire 64-bit source is zero and x1 is not read. An 8-byte-aligned Zilsd access cannot raise address-misaligned, but the doubleword access need not be atomic. At addresses divisible by 4, each word access must be atomic; 4-byte alignment without 8-byte alignment may still trap.
SD Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rs2
imm
rs1
sd,()
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Assumes writable ordinary little-endian memory. Success stores the low 64 bits and advances PC by 4; general permissions, partial writes and device side effects are not modeled. Misaligned exceptions do not guarantee unchanged memory.
a0(x10)
0x0000000000001000
t0(x5)
0x0000000000003001
PC
0x0000000000002000
This EEI branch applies only when the effective address is not divisible by 8; a naturally aligned access must not raise an address-misaligned exception.
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
00101
rs2
01010
rs1
011
funct3
00000
imm[4:0]
0100011
opcode
Execution Data Path
instruction
0x00553023
opcode
0100011 -> STORE
funct3
011 -> SD
rs2 / base
t0(x5)=0x0000000000003001 / a0(x10)=0x0000000000001000
S-imm
imm[11:5]|imm[4:0] -> 0; ea=0x0000000000001000 (naturally aligned (8-byte))
store data
Not computed
memory
pc = 0x0000000000002000; store not committed
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00553023
syntax : sd x5, 0(x10)
Pending result: Not computed
Current architectural state
pc = 0x0000000000002000; store not committed
This SD animation models only the RV64I single-register 64-bit store. RV32 Zilsd uses the same mnemonic and encoding but operates on an even/odd register pair; its distinct conditions are covered in the static page content.
Quick Understanding & Search Notes
RV64I SD stores one 64-bit register; RV32 Zilsd SD stores an even/odd register pair. Keep these source models distinct.
The signed 12-bit byte offset ranges from -2048 through 2047; imm[11:5] is at inst[31:25], and imm[4:0] at inst[11:7].
Odd rs2 encodings are reserved in RV32 Zilsd; rs2=x0 specially supplies an entire 64-bit zero value.
RV64I misaligned accesses are EEI-defined. Zilsd does not guarantee whole-doubleword atomicity, and decomposed accesses can cause partial writes.
Common Usage Scenarios
Doubleword data storage
SD stores the source at this page's data width; check the address, region permissions, and applicable RV64I/Zilsd conditions.
RV32 Zilsd register-pair storage
SD stores the source at this page's data width; check the address, region permissions, and applicable RV64I/Zilsd conditions.
Pre-Use Checklist
Syntax Check
- Use rs2, offset(rs1); the signed 12-bit byte offset ranges from -2048 through 2047, split across inst[31:25] and inst[11:7].
Semantic Check
- RV64I: store the 64-bit value in rs2; RV32 Zilsd: store a 64-bit value from an even/odd register pair.
- Distinguish RV64I single-register stores from RV32 Zilsd even/odd pairs; Zilsd rs2=x0 supplies an entire 64-bit zero source.
Pitfalls / Common Confusions
RV64I semantics store one 64-bit register; RV32 Zilsd semantics store an even/odd register pair.
Under Zilsd, rs2 must be even; odd rs2 encodings are reserved.
The offset is a sign-extended 12-bit immediate; 8-byte natural alignment is the most portable case.