RISC-V SD Instruction Details
Instruction ManualS-typeRV64I: store the 64-bit value in rs2; RV32 Zilsd: store a 64-bit value from an even/odd register pair.
Instruction Syntax
Instruction Encoding
SD uses opcode 0100011 (0x23), funct3 011. The rs1 field holds the base address, rs2 holds the store data, and the 12-bit immediate split across imm[11:5] and imm[4:0] provides the offset.
Instruction Behavior
In RV64I, SD is an S-type instruction (opcode=0100011, funct3=011) that stores the 64-bit value in rs2 to rs1 plus a sign-extended 12-bit offset. In the RV32 Zilsd extension, the same mnemonic/encoding means store doubleword from a register pair: the 64-bit value comes from rs2 and rs2+1, and rs2 must be even. Natural alignment is an 8-byte address; under Zilsd, a 4-byte-aligned but not 8-byte-aligned access may be decomposed into two atomic word accesses and may still raise a misaligned trap.
Common Usage Scenarios
Understand this scenario with real code like «sd x10, 24(x2) # store 64-bit value to stack at offset 24».
Understand this scenario with real code like «sd x10, 24(x2) # store 64-bit value to stack at offset 24».
Pre-Use Checklist
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.