RISC-V SD Instruction Details
Instruction ManualS-typeRV64I: store the 64-bit value in rs2; RV32 Zilsd: store a 64-bit value from an even/odd register pair.
Instruction Syntax
Instruction Behavior
In RV64I, SD is an S-type instruction (opcode=0100011, funct3=011) that stores the low 64 bits of rs2 to rs1 plus a sign-extended 12-bit offset. In the RV32 Zilsd extension, the same mnemonic/encoding means store doubleword from a register pair: the 64-bit value comes from rs2 and rs2+1, and rs2 must be even. An 8-byte-aligned Zilsd access cannot raise an address-misaligned exception but need not be atomic; when the effective address is a multiple of 4, each word access must be atomic and a misaligned trap remains possible.
SD Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This EEI branch applies only when the effective address is not divisible by 8; a naturally aligned access must not raise an address-misaligned exception.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This SD animation models only the RV64I single-register 64-bit store. RV32 Zilsd uses the same mnemonic and encoding but operates on an even/odd register pair; its distinct conditions are covered in the static page content.
Common Usage Scenarios
Understand this scenario with real code like «sd x10, 24(x2) # store 64-bit value to stack at offset 24».
Understand this scenario with real code like «sd x10, 24(x2) # store 64-bit value to stack at offset 24».
Pre-Use Checklist
- Verify store source rs2 and base address rs1 registers.
- Confirm immediate offset (imm[11:5] | imm[4:0]) is split correctly.
- Check the target memory address alignment requirement.
- Ensure the write does not corrupt caller-saved registers.