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RISC-V SW Instruction Details

Instruction ManualS-type

Store the low 32 bits of rs2 to the effective memory address

Instruction Syntax

sw rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IRV64IMemory Store
Related Search Terms
SW instructionRISC-V SWsw syntaxsw encodingsw S-typeSW store wordsw store

Instruction Behavior

SW (S-type, opcode=0100011, funct3=010) stores the low 32 bits of rs2 to the effective address (rs1 + sign-extended 12-bit offset). Naturally aligned word addresses are multiples of 4; the EEI defines whether a misaligned access completes or raises an exception. SW is available in RV32I and RV64I.

SW Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs2
imm
rs1
sw
,
(
)
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

The example assumes writable ordinary little-endian memory. Successful accesses show the low 32-bit word and PC+4; misaligned exceptions do not imply unchanged memory, and partial writes or side effects are not modeled.

a0(x10)
0x00001000
t0(x5)
0x00003001
PC
0x00002000

This EEI branch applies only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.

31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
00101
rs2
01010
rs1
010
funct3
00000
imm[4:0]
0100011
opcode
Execution Data Path
instruction
0x00552023
opcode
0100011 -> STORE
funct3
010 -> SW
rs2 / base
t0(x5)=0x00003001 / a0(x10)=0x00001000
S-imm
imm[11:5]|imm[4:0] -> 0; ea=0x00001000 (naturally aligned (4-byte))
store data
Not computed
memory
pc = 0x00002000; store not committed
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00552023
syntax : sw x5, 0(x10)
Pending result: Not computed
Current architectural state
pc = 0x00002000; store not committed

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

SW forms the effective address as rs1 plus a signed 12-bit offset and stores the low 32 bits of rs2 to memory.

The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW. A naturally aligned 4-byte SW cannot raise an address-misaligned exception; the EEI defines the misaligned result.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120, §2.6 / §4.3

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Data Storing

Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».

Pre-Use Checklist

Syntax Check
  • Register operands select x0 through x31; ABI register names are aliases for these registers.
  • SW uses rs2, offset(rs1); the signed byte offset ranges from -2048 through 2047 and is split into S-type imm[11:5] and imm[4:0].
Semantic Check
  • The effective address is rs1 plus the sign-extended offset, wrapping to XLEN; a successful access stores the low 32 bits of rs2 without writing general registers.
  • A naturally aligned 4-byte access must not raise address-misaligned; the EEI determines misaligned completion or exceptions.

Pitfalls / Common Confusions

A naturally aligned 4-byte access cannot raise an address-misaligned exception; the EEI defines whether a misaligned access completes or raises address-misaligned or access-fault
Only the low 32 bits of rs2 are written; on RV64 this is not the full XLEN-wide register

FAQ

Does SW store the whole register?

SW stores only the low 32 bits of rs2, not necessarily the full XLEN-wide register.

How is the store address computed?

The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.