Effective Address
Store instructions form the effective byte address by adding rs1 to a sign-extended 12-bit offset. SW uses the same -2048 to 2047 offset range.
RISC-V Unprivileged ISA, RV32I load and store instructionsSW
RISC-V SW Instruction Details
Instruction ManualS-typeStore the full 32-bit value of rs2 to memory
Instruction Syntax
sw rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IRV64IMemory Store
Related Search Terms
Instruction Behavior
SW (S-type, opcode=0100011, funct3=010) stores the low 32 bits of rs2 to the effective address (rs1 + sign-extended 12-bit offset). Naturally aligned word addresses are multiples of 4; the EEI defines whether a misaligned access completes or raises an exception. SW is available in RV32I and RV64I.
SW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rs2
imm
rs1
sw,()
Execution Context
a0(x10)
0x00001000
This EEI branch applies only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
00101
rs2
01010
rs1
010
funct3
00000
imm[4:0]
0100011
opcode
Execution Data Path
instruction
0x00552023
opcode
0100011 -> STORE
funct3
010 -> SW
rs2 / base
t0(x5)=0x00003001 / a0(x10)=0x00001000
S-imm
imm[11:5]|imm[4:0] -> 0; ea=0x00001000 (naturally aligned (4-byte))
store data
select low 32 bits -> 0x00003001
memory
mem[0x00001000] = 0x00003001
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00552023
syntax : sw t0(x5), 0(a0(x10))
result : mem[0x00001000] = 0x00003001
Architectural Result
mem[0x00001000] = 0x00003001
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SW forms the effective address as rs1 plus a signed 12-bit offset and stores the low 32 bits of rs2 to memory.
The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW. A naturally aligned 4-byte SW cannot raise an address-misaligned exception; the EEI defines the misaligned result.
Official Spec Notes
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Stored Width
SW stores the low 32 bits of rs2 to memory; it does not store the full XLEN-wide register value.
RISC-V Unprivileged ISA, RV32I load and store instructionsCommon Usage Scenarios
Data Storing
Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».
Register Operations
Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».
Stack & Frame
Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».
Pre-Use Checklist
Syntax Check
- Verify store source rs2 and base address rs1 registers.
- Confirm immediate offset (imm[11:5] | imm[4:0]) is split correctly.
Semantic Check
- Check the target memory address alignment requirement.
- Ensure the write does not corrupt caller-saved registers.
Pitfalls / Common Confusions
A naturally aligned 4-byte access cannot raise an address-misaligned exception; the EEI defines whether a misaligned access completes or raises address-misaligned or access-fault
Only the low 32 bits of rs2 are written; on RV64 this is not the full XLEN-wide register
FAQ
Does SW store the whole register?
SW stores only the low 32 bits of rs2, not necessarily the full XLEN-wide register.
How is the store address computed?
The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.