Effective Address
Store instructions form the effective byte address by adding rs1 to a sign-extended 12-bit offset. SW uses the same -2048 to 2047 offset range.
RISC-V Unprivileged ISA, RV32I load and store instructionsSW
RISC-V SW Instruction Details
Instruction ManualS-typeStore the full 32-bit value of rs2 to memory
Instruction Syntax
sw rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IMemory Store
Related Search Terms
Instruction Encoding
31..25
imm[11:5]
24..20
rs2
19..15
rs1
14..12
funct3
11..7
imm[4:0]
6..0
opcode
SW uses opcode 0100011 (0x23), funct3 010. The rs1 field holds the base address, rs2 holds the store data, and the 12-bit immediate split across imm[11:5] and imm[4:0] provides the offset.
Format: S-type
opcode: 0100011 (0x23)
funct3: 010 (0x2)
Instruction Behavior
SW (S-type, opcode=0100011, funct3=010) stores the low 32 bits of rs2 to the effective address (rs1 + sign-extended 12-bit offset). Naturally aligned word addresses are multiples of 4. This is the primary store instruction in RV32I, used to save register values to memory.
Quick Understanding & Search Notes
SW forms the effective address as rs1 plus a signed 12-bit offset and stores the low 32 bits of rs2 to memory.
The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW.
Official Spec Notes
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Stored Width
SW stores the low 32 bits of rs2 to memory; it does not store the full XLEN-wide register value.
RISC-V Unprivileged ISA, RV32I load and store instructionsCommon Usage Scenarios
Data Storing
Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».
Register Operations
Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».
Stack & Frame
Understand this scenario with real code like «sw x5, 0(x10) # mem[x10+0][31:0] = x5[31:0]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Natural alignment requires address multiple of 4
Only the low 32 bits of rs2 are written; on RV64 this is not the full XLEN-wide register
FAQ
Does SW store the whole register?
SW stores only the low 32 bits of rs2, not necessarily the full XLEN-wide register.
How is the store address computed?
The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.