Does SB store the whole register?
SB stores only the low 8 bits of rs2, not necessarily the full XLEN-wide register.
SB
RISC-V SB Instruction Details
Instruction ManualS-typeStore the low 8 bits of rs2 to memory
Instruction Syntax
sb rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IMemory Store
Related Search Terms
Instruction Behavior
SB (S-type, opcode=0100011, funct3=000) stores the low 8 bits of rs2 to the effective address (rs1 + sign-extended 12-bit offset). The S-type immediate is split: upper 7 bits at inst[11:5], lower 5 bits at inst[4:0]. Misaligned access behavior is EEI-defined.
SB Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rs2
imm
rs1
sb,()
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
00101
rs2
01010
rs1
000
funct3
00000
imm[4:0]
0100011
opcode
Execution Data Path
instruction
0x00550023
opcode
0100011 -> STORE
funct3
000 -> SB
rs2 / base
t0(x5)=0x00003001 / a0(x10)=0x00001000
S-imm
imm[11:5]|imm[4:0] -> 0; ea=0x00001000
store data
select low 8 bits -> 0x00000001
memory
mem[0x00001000] = 0x00000001
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00550023
syntax : sb t0(x5), 0(a0(x10))
result : mem[0x00001000] = 0x00000001
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SB forms the effective address as rs1 plus a signed 12-bit offset and stores the low 8 bits of rs2 to memory.
The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «sb x5, 0(x10) # mem[x10+0][7:0] = x5[7:0]».
Data Storing
Understand this scenario with real code like «sb x5, 0(x10) # mem[x10+0][7:0] = x5[7:0]».
Register Operations
Understand this scenario with real code like «sb x5, 0(x10) # mem[x10+0][7:0] = x5[7:0]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only low 8 bits of rs2 are stored; upper bits ignored
S-type immediate split encoding requires attention
FAQ
How is the store address computed?
The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.