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LBU

RISC-V LBU Instruction Details

Instruction ManualI-type

Load an 8-bit byte from memory, zero-extend it to XLEN, and write rd

Instruction Syntax

lbu rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IRV64IMemory Load
Related Search Terms
LBU instructionRISC-V LBUlbu syntaxlbu encodinglbu I-typeLBU vs LBlbu load

Instruction Behavior

LBU is an RV32I/RV64I I-type load (opcode=0000011, funct3=100). Its effective address is rs1 plus a sign-extended 12-bit offset; it reads 8 bits there, zero-extends the value to XLEN, and writes rd. LB sign-extends whereas LBU zero-extends.

LBU Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
imm
rs1
lbu
,
(
)
Execution Context
a0(x10)
0x00001000
mem[0x00001000]
0x000000F2
31..20
19..15
14..12
11..7
6..0
000000000000
imm[11:0]
01010
rs1
100
funct3
00101
rd
0000011
opcode
Execution Data Path
instruction
0x00054283
opcode
0000011 -> LOAD
funct3
100 -> LBU
rd / base
t0(x5) / a0(x10)=0x00001000
offset
000000000000 -> 0; ea=0x00001000 (naturally aligned (1-byte))
load
8-bit 0x000000F2 -> zero extend
x5
t0(x5) = 0x000000F2
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00054283
syntax : lbu t0(x5), 0(a0(x10))
result : t0(x5) = 0x000000F2
Architectural Result
t0(x5) = 0x000000F2

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

LBU reads a 8-bit byte from the effective address formed by rs1 plus a signed 12-bit offset, then zero-extends the value into rd.

All base loads form an effective byte address as rs1 plus a sign-extended 12-bit offset.
Naturally aligned accesses should not raise address-misaligned exceptions; misaligned behavior depends on the execution environment interface.
RISC-V Unprivileged ISA Manual: RV32I/RV64I Base Integer Loads and Stores

Common Usage Scenarios

Data Loading

Understand this scenario with real code like «lbu x7, 0(x10) # x7 = zero_ext(mem[x10+0][7:0])».

Network & Byte Order

Understand this scenario with real code like «lbu x7, 0(x10) # x7 = zero_ext(mem[x10+0][7:0])».

Type Conversion

Understand this scenario with real code like «lbu x7, 0(x10) # x7 = zero_ext(mem[x10+0][7:0])».

Pre-Use Checklist

Syntax Check
  • Verify the immediate field is within the valid range.
  • Confirm source register rs1 points to the correct operand.
Semantic Check
  • Check if the immediate sign-extension matches expectations.
  • Ensure the result register rd has a clear purpose.

Pitfalls / Common Confusions

vs LB: zero-extension vs sign-extension
Use LB if signed value is actually needed

FAQ

What offset range does LBU use?

Base load instructions use a sign-extended 12-bit byte offset, typically -2048 through 2047.

What is the difference between signed and unsigned loads?

LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.