What offset range does LHU use?
The signed 12-bit byte offset encodes exactly -2048 through 2047.
LHU
RISC-V LHU Instruction Details
Instruction ManualI-typeLoad a 16-bit halfword from memory, zero-extend it to XLEN, and write rd
Instruction Syntax
lhu rd, offset(rs1)
Operand Breakdown
rd: receives the 16-bit load zero-extended to XLEN after a successful access; rd=x0 discards only writeback, with applicable exceptions and other side effects retained.
rs1: memory base, read before writeback; offset: sign-extended 12-bit byte displacement from -2048 through 2047.
The effective address is rs1+offset truncated to XLEN; 2-byte natural alignment must not raise address-misaligned, while misaligned outcomes depend on the EEI.
RV32IRV64IMemory Load
Related Search Terms
Instruction Behavior
LHU (I-type, opcode=0000011, funct3=101) reads a 16-bit halfword from the effective byte address rs1 plus a sign-extended 12-bit offset, zero-extends it to XLEN, and writes rd. A naturally aligned halfword address is a multiple of 2; the EEI defines completion or an exception for a misaligned access. Unlike LH, LHU zero-extends.
LHU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
imm
rs1
lhu,()
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Assumes readable ordinary memory, with the displayed sample value at each selected effective address. Only misaligned EEI outcomes are modeled, not permissions or device side effects. Byte accesses are always naturally aligned; successful loads advance PC by 4, while exceptions stop ordinary writeback.
a0(x10)
0x00001000
mem[0x00001002]
0x0000FFF2
This EEI branch applies only when the effective address is not divisible by 2; a naturally aligned access must not raise an address-misaligned exception.
31..20
19..15
14..12
11..7
6..0
000000000010
imm[11:0]
01010
rs1
101
funct3
00101
rd
0000011
opcode
Execution Data Path
instruction
0x00255283
opcode
0000011 -> LOAD
funct3
101 -> LHU
rd / base
t0(x5) / a0(x10)=0x00001000
offset
000000000010 -> 2; ea=0x00001002 (naturally aligned (2-byte))
load
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00255283
syntax : lhu t0(x5), 2(a0(x10))
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
LHU reads a 16-bit halfword from the effective address formed by rs1 plus a signed 12-bit offset, then zero-extends the value into rd.
Base loads form an effective byte address from rs1 plus a sign-extended 12-bit offset; LHU zero-extends the loaded 16-bit value to XLEN.
Naturally aligned accesses shall not raise address-misaligned exceptions; the EEI defines completion, address-misaligned exception, or access-fault behavior for a misaligned access.
Common Usage Scenarios
Unsigned Halfword Load
Understand this scenario with real code like «lhu x8, 2(x10) # x8 = zero_ext(mem[x10+2][15:0])».
Pre-Use Checklist
Syntax Check
- Use rd, offset(rs1), with a signed 12-bit byte offset from -2048 through 2047; LWU is RV64I-only.
Semantic Check
- Truncate rs1 plus sign-extended offset to XLEN for the address; LHU zero-extends 16 bits and LWU zero-extends 32 bits.
- Natural alignment must not raise address-misaligned; the EEI determines misaligned completion or exceptions. rd=x0 retains applicable exceptions and other side effects.
Pitfalls / Common Confusions
vs LH: zero-extension vs sign-extension
Natural alignment requires address multiple of 2
FAQ
What is the difference between signed and unsigned loads?
LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.