What offset range does LHU use?
Base load instructions use a sign-extended 12-bit byte offset, typically -2048 through 2047.
LHU
RISC-V LHU Instruction Details
Instruction ManualI-typeLoad a 16-bit halfword from memory, zero-extend it to XLEN, and write rd
Instruction Syntax
lhu rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IRV64IMemory Load
Related Search Terms
Instruction Behavior
LHU (I-type, opcode=0000011, funct3=101) reads a 16-bit halfword from the effective byte address rs1 plus a sign-extended 12-bit offset, zero-extends it to XLEN, and writes rd. A naturally aligned halfword address is a multiple of 2; the EEI defines completion or an exception for a misaligned access. Unlike LH, LHU zero-extends.
LHU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
imm
rs1
lhu,()
Execution Context
a0(x10)
0x00001000
mem[0x00001002]
0x0000FFF2
This EEI branch applies only when the effective address is not divisible by 2; a naturally aligned access must not raise an address-misaligned exception.
31..20
19..15
14..12
11..7
6..0
000000000010
imm[11:0]
01010
rs1
101
funct3
00101
rd
0000011
opcode
Execution Data Path
instruction
0x00255283
opcode
0000011 -> LOAD
funct3
101 -> LHU
rd / base
t0(x5) / a0(x10)=0x00001000
offset
000000000010 -> 2; ea=0x00001002 (naturally aligned (2-byte))
load
16-bit 0x0000FFF2 -> zero extend
x5
t0(x5) = 0x0000FFF2
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00255283
syntax : lhu t0(x5), 2(a0(x10))
result : t0(x5) = 0x0000FFF2
Architectural Result
t0(x5) = 0x0000FFF2
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
LHU reads a 16-bit halfword from the effective address formed by rs1 plus a signed 12-bit offset, then zero-extends the value into rd.
Base loads form an effective byte address from rs1 plus a sign-extended 12-bit offset; LHU zero-extends the loaded 16-bit value to XLEN.
Naturally aligned accesses shall not raise address-misaligned exceptions; the EEI defines completion, address-misaligned exception, or access-fault behavior for a misaligned access.
Common Usage Scenarios
Network & Byte Order
Understand this scenario with real code like «lhu x8, 2(x10) # x8 = zero_ext(mem[x10+2][15:0])».
Type Conversion
Understand this scenario with real code like «lhu x8, 2(x10) # x8 = zero_ext(mem[x10+2][15:0])».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
vs LH: zero-extension vs sign-extension
Natural alignment requires address multiple of 2
FAQ
What is the difference between signed and unsigned loads?
LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.