RISC-V LW Instruction Details

Instruction ManualI-type

Load a 32-bit word from memory into rd

Instruction Syntax

lw rd, offset(rs1)

Operand Breakdown

rd: receives the 32-bit word sign-extended to XLEN after a successful access; rd=x0 only discards writeback, while applicable exceptions and other side effects still occur.

rs1: provides the memory base using its value before writeback.

imm: signed byte offset from -2048 through 2047; truncate rs1 plus sign-extended imm to XLEN for the effective address. Naturally aligned accesses must not raise address-misaligned exceptions; misaligned outcomes depend on the EEI.

RV32IRV64IMemory Load

Related Search Terms

LW instruction RISC-V LW lw syntax lw encoding lw I-type LW vs LWU lw load

Instruction Behavior

LW uses I-type encoding (opcode=0000011, funct3=010). Its effective byte address is rs1 plus a sign-extended 12-bit offset, wrapping to XLEN bits. A successful access loads a 32-bit word, sign-extends it to XLEN, and writes rd. Naturally aligned word addresses are divisible by 4 and must not raise an address-misaligned exception; misaligned completion or exceptions are EEI-defined. rd=x0 discards only the loaded value and must still report any applicable exceptions and cause any applicable other side effects.

LW Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

imm

rs1

(

)

Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

The example assumes readable ordinary little-endian memory. Each selected address uses the sample bytes 02 00 00 80 (word 0x80000002). Only the EEI outcome of misalignment is selected; general permissions and device side effects are outside this example.

a0(x10)

0x00001000

mem[0x00001000]

0x80000002

XLENMisaligned EEI result

This EEI branch applies only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.

31..20

19..15

14..12

11..7

6..0

000000000000

imm[11:0]

01010

rs1

010

funct3

00101

0000011

opcode

Execution Data Path

instruction

0x00052283

opcode

0000011 -> LOAD

funct3

010 -> LW

rd / base

t0(x5) / a0(x10)=0x00001000

offset

000000000000 -> sign_extend(0)=0x00000000

load

Not computed

t0(x5) = 0x00003001; pc = 0x00002000

Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00052283

syntax : lw x5, 0(x10)

Pending result: Not computed

Current architectural state

t0(x5) = 0x00003001; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

LW reads a 32-bit word from the effective address formed by rs1 plus a signed 12-bit offset, then sign-extends the value to XLEN and writes rd.

All base loads form an effective byte address as rs1 plus a sign-extended 12-bit offset.

An effective address divisible by 4 is naturally aligned and must not raise an address-misaligned exception; misaligned behavior depends on the execution environment interface.

The LW example assumes a successful read from ordinary little-endian memory: bytes 02 00 00 80 starting at address 0x1000 form the word 0x80000002.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Official Release 20260120, §2.6 The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Official Release 20260120, §4.3

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Effective Address

LW adds a sign-extended 12-bit offset to rs1, wrapping to XLEN bits, to form its effective byte address. An address divisible by 4 is naturally aligned and must not raise an address-misaligned exception; the EEI defines misaligned completion or exceptions.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, version 20260120, §2.6 Load and Store Instructions

Sign Extension

LW loads a 32-bit value from memory and sign-extends it to XLEN before writing rd. On RV64, use LWU when a zero-extended 32-bit load is required.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, version 20260120, §2.6 Load and Store Instructions; §4.3 Load and Store Instructions

Common Usage Scenarios

Data Loading

RV32I/RV64I example: s0=0x1008; 0x1000 is readable, naturally aligned ordinary little-endian memory containing 02 00 00 80. lw a0, -8(s0) produces 0x80000002 on RV32 and 0xffffffff80000002 on RV64.

Pre-Use Checklist

Syntax Check

Register operands select x0 through x31; ABI register names are aliases for those registers.
The signed 12-bit immediate encodes -2048 through 2047, including both endpoints.

Semantic Check

The effective address is rs1 plus the sign-extended byte offset, truncated to XLEN; a successful access sign-extends the loaded 32-bit word to XLEN.
Naturally aligned accesses must not raise address-misaligned exceptions; misaligned outcomes depend on the EEI. rd=x0 still incurs applicable exceptions and other side effects.

Pitfalls / Common Confusions

A word address divisible by 4 is naturally aligned and must not raise an address-misaligned exception; the EEI defines the behavior of misaligned accesses

rd=x0 still performs the access; discarding the destination does not suppress applicable exceptions or other side effects

FAQ

What offset range does LW use?

Base load instructions use a sign-extended 12-bit byte offset with the exact encodable range -2048 through 2047.

What is the difference between signed and unsigned loads?

LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.