Load a 32-bit word from memory into rd
LW uses opcode 0000011 (0x03), funct3 010. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
LW (I-type, opcode=0000011, funct3=010) loads a 32-bit word from memory at the effective address (rs1 + sign-extended 12-bit offset), sign-extends it to XLEN, and writes it to rd. Naturally aligned word addresses are multiples of 4. When rd=x0, exceptions and side effects still occur even though value is discarded. This is the primary load instruction in RV32I.
LW reads a 32-bit word from the effective address formed by rs1 plus a signed 12-bit offset, then sign-extends the value to XLEN and writes rd.
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
Load instructions form the effective byte address by adding rs1 to a sign-extended 12-bit offset; alignment requirements and misaligned behavior depend on the EEI/implementation.
RISC-V Unprivileged ISA, RV32I load and store instructionsLW loads a 32-bit value from memory and sign-extends it to XLEN before writing rd. On RV64, use LWU when a zero-extended 32-bit load is required.
RISC-V Unprivileged ISA, RV32I load and store instructionsUnderstand this scenario with real code like «lw x5, 0(x10) # x5 = mem[x10+0][31:0]».
Understand this scenario with real code like «lw x5, 0(x10) # x5 = mem[x10+0][31:0]».
Base load instructions use a sign-extended 12-bit byte offset, typically -2048 through 2047.
LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.