RVOPcode
Home/Instructions/Load Byte
LB

RISC-V LB Instruction Details

Instruction ManualI-type

Load a byte from memory, sign-extend to 32 bits, and write to rd

Instruction Syntax

lb rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IMemory Load
Related Search Terms
LB instructionRISC-V LBlb syntaxlb encodinglb I-typeLB vs LBUlb load

Instruction Encoding

31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

LB uses opcode 0000011 (0x03), funct3 000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.

Format: I-type
opcode: 0000011 (0x03)
funct3: 000 (0x0)

Instruction Behavior

LB (I-type, opcode=0000011, funct3=000) loads an 8-bit byte from memory at the effective address (rs1 + sign-extended 12-bit offset), sign-extends it to 32 bits, and writes to rd. Misaligned access behavior depends on the EEI.

Quick Understanding & Search Notes

LB reads a 8-bit byte from the effective address formed by rs1 plus a signed 12-bit offset, then sign-extends the value into rd.

All base loads form an effective byte address as rs1 plus a sign-extended 12-bit offset.
Naturally aligned accesses should not raise address-misaligned exceptions; misaligned behavior depends on the execution environment interface.
RISC-V Unprivileged ISA Manual: RV32I Base Integer Instruction Set

Common Usage Scenarios

Data Loading

Understand this scenario with real code like «lb x5, 0(x10) # x5 = sign_ext(mem[x10+0][7:0])».

Type Conversion

Understand this scenario with real code like «lb x5, 0(x10) # x5 = sign_ext(mem[x10+0][7:0])».

Network & Byte Order

Understand this scenario with real code like «lb x5, 0(x10) # x5 = sign_ext(mem[x10+0][7:0])».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Sign extension: if byte MSB=1, upper bits filled with 1
Behavior of misaligned addresses is EEI-dependent

FAQ

What offset range does LB use?

Base load instructions use a sign-extended 12-bit byte offset, typically -2048 through 2047.

What is the difference between signed and unsigned loads?

LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.