What offset range does LH use?
Base load instructions use a sign-extended 12-bit byte offset, typically -2048 through 2047.
LH
RISC-V LH Instruction Details
Instruction ManualI-typeLoad a 16-bit halfword from memory, sign-extend it to XLEN, and write rd
Instruction Syntax
lh rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV32IRV64IMemory Load
Related Search Terms
Instruction Behavior
LH is an RV32I/RV64I I-type load (opcode=0000011, funct3=001). Its effective address is rs1 plus a sign-extended 12-bit offset; it reads 16 bits there, sign-extends the value to XLEN, and writes rd. A naturally aligned halfword address is a multiple of 2; misaligned-access behavior is EEI-defined.
LH Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
imm
rs1
lh,()
Execution Context
a0(x10)
0x00001000
mem[0x00001002]
0x0000FFF2
This EEI branch applies only when the effective address is not divisible by 2; a naturally aligned access must not raise an address-misaligned exception.
31..20
19..15
14..12
11..7
6..0
000000000010
imm[11:0]
01010
rs1
001
funct3
00101
rd
0000011
opcode
Execution Data Path
instruction
0x00251283
opcode
0000011 -> LOAD
funct3
001 -> LH
rd / base
t0(x5) / a0(x10)=0x00001000
offset
000000000010 -> 2; ea=0x00001002 (naturally aligned (2-byte))
load
16-bit 0x0000FFF2 -> sign extend
x5
t0(x5) = 0xFFFFFFF2
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00251283
syntax : lh t0(x5), 2(a0(x10))
result : t0(x5) = 0xFFFFFFF2
Architectural Result
t0(x5) = 0xFFFFFFF2
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
LH reads a 16-bit halfword from the effective address formed by rs1 plus a signed 12-bit offset, then sign-extends the value into rd.
All base loads form an effective byte address as rs1 plus a sign-extended 12-bit offset.
Naturally aligned accesses should not raise address-misaligned exceptions; misaligned behavior depends on the execution environment interface.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «lh x6, 4(x10) # x6 = sign_ext(mem[x10+4][15:0])».
Network & Byte Order
Understand this scenario with real code like «lh x6, 4(x10) # x6 = sign_ext(mem[x10+4][15:0])».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
Natural alignment requires address multiple of 2
vs LHU: sign-extension vs zero-extension
FAQ
What is the difference between signed and unsigned loads?
LB/LH/LW sign-extend the loaded value to XLEN; LBU/LHU zero-extend. On RV64, use LWU when a 32-bit word should be zero-extended.