Does SH store the whole register?
SH stores only the low 16 bits of rs2, not necessarily the full XLEN-wide register.
SH
RISC-V SH Instruction Details
Instruction ManualS-typeStore the low 16 bits of rs2 to memory
Instruction Syntax
sh rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IRV64IMemory Store
Related Search Terms
Instruction Behavior
SH uses a 32-bit S-type encoding (opcode=0100011, funct3=001) to store rs2's low 16 bits. The effective byte address is rs1 plus a sign-extended 12-bit offset, wrapping to XLEN bits; the offset ranges from -2048 through 2047. imm[11:5] occupies inst[31:25], and imm[4:0] occupies inst[11:7]. Addresses divisible by 2 are naturally aligned; the EEI defines whether a misaligned access completes or raises address-misaligned/access-fault.
SH Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rs2
imm
rs1
sh,()
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Assumes writable ordinary little-endian memory. Success stores the low 16 bits and advances PC by 4; general permissions, partial writes and device side effects are not modeled. Misaligned exceptions do not guarantee unchanged memory.
a0(x10)
0x00001000
t0(x5)
0x00003001
PC
0x00002000
This EEI branch applies only when the effective address is not divisible by 2; a naturally aligned access must not raise an address-misaligned exception.
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
00101
rs2
01010
rs1
001
funct3
00000
imm[4:0]
0100011
opcode
Execution Data Path
instruction
0x00551023
opcode
0100011 -> STORE
funct3
001 -> SH
rs2 / base
t0(x5)=0x00003001 / a0(x10)=0x00001000
S-imm
imm[11:5]|imm[4:0] -> 0; ea=0x00001000 (naturally aligned (2-byte))
store data
Not computed
memory
pc = 0x00002000; store not committed
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00551023
syntax : sh x5, 0(x10)
Pending result: Not computed
Current architectural state
pc = 0x00002000; store not committed
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SH forms the effective address as rs1 plus a signed 12-bit offset and stores the low 16 bits of rs2 to memory.
The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW.
Common Usage Scenarios
Halfword data storage
SH stores the source at this page's data width; check the address, region permissions, and applicable RV32I/RV64I conditions.
Pre-Use Checklist
Syntax Check
- Use rs2, offset(rs1); the signed 12-bit byte offset ranges from -2048 through 2047, split across inst[31:25] and inst[11:7].
Semantic Check
- Store the low 16 bits of rs2 to memory
- Address calculation wraps to XLEN; no GPR is written. Byte accesses are always naturally aligned, while halfword misaligned outcomes are EEI-defined.
Pitfalls / Common Confusions
Only low 16 bits of rs2 are stored
Natural alignment requires address multiple of 2
FAQ
How is the store address computed?
The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.