Does SH store the whole register?
SH stores only the low 16 bits of rs2, not necessarily the full XLEN-wide register.
SH
RISC-V SH Instruction Details
Instruction ManualS-typeStore the low 16 bits of rs2 to memory
Instruction Syntax
sh rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IRV64IMemory Store
Related Search Terms
Instruction Behavior
SH (S-type, opcode=0100011, funct3=001) stores the low 16 bits of rs2 to the effective address (rs1 + a sign-extended 12-bit offset). A naturally aligned halfword address is a multiple of 2; the EEI defines whether a misaligned access completes or raises an exception.
SH Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rs2
imm
rs1
sh,()
Execution Context
a0(x10)
0x00001000
This EEI branch applies only when the effective address is not divisible by 2; a naturally aligned access must not raise an address-misaligned exception.
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
00101
rs2
01010
rs1
001
funct3
00000
imm[4:0]
0100011
opcode
Execution Data Path
instruction
0x00551023
opcode
0100011 -> STORE
funct3
001 -> SH
rs2 / base
t0(x5)=0x00003001 / a0(x10)=0x00001000
S-imm
imm[11:5]|imm[4:0] -> 0; ea=0x00001000 (naturally aligned (2-byte))
store data
select low 16 bits -> 0x00003001
memory
mem[0x00001000] = 0x00003001
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00551023
syntax : sh t0(x5), 0(a0(x10))
result : mem[0x00001000] = 0x00003001
Architectural Result
mem[0x00001000] = 0x00003001
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SH forms the effective address as rs1 plus a signed 12-bit offset and stores the low 16 bits of rs2 to memory.
The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «sh x6, 2(x10) # mem[x10+2][15:0] = x6[15:0]».
Data Storing
Understand this scenario with real code like «sh x6, 2(x10) # mem[x10+2][15:0] = x6[15:0]».
Pre-Use Checklist
Syntax Check
- Verify store source rs2 and base address rs1 registers.
- Confirm immediate offset (imm[11:5] | imm[4:0]) is split correctly.
Semantic Check
- Check the target memory address alignment requirement.
- Ensure the write does not corrupt caller-saved registers.
Pitfalls / Common Confusions
Only low 16 bits of rs2 are stored
Natural alignment requires address multiple of 2
FAQ
How is the store address computed?
The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.