Does SH store the whole register?
SH stores only the low 16 bits of rs2, not necessarily the full XLEN-wide register.
SH
RISC-V SH Instruction Details
Instruction ManualS-typeStore the low 16 bits of rs2 to memory
Instruction Syntax
sh rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
RV32IMemory Store
Related Search Terms
Instruction Encoding
31..25
imm[11:5]
24..20
rs2
19..15
rs1
14..12
funct3
11..7
imm[4:0]
6..0
opcode
SH uses opcode 0100011 (0x23), funct3 001. The rs1 field holds the base address, rs2 holds the store data, and the 12-bit immediate split across imm[11:5] and imm[4:0] provides the offset.
Format: S-type
opcode: 0100011 (0x23)
funct3: 001 (0x1)
Instruction Behavior
SH (S-type, opcode=0100011, funct3=001) stores the low 16 bits of rs2 to the effective address (rs1 + sign-extended 12-bit offset). Naturally aligned halfword addresses are multiples of 2.
Quick Understanding & Search Notes
SH forms the effective address as rs1 plus a signed 12-bit offset and stores the low 16 bits of rs2 to memory.
The S-type immediate is split across two instruction fields, but semantically it is one signed 12-bit byte offset.
Store instructions do not write rd; the stored width is selected by SB/SH/SW.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «sh x6, 2(x10) # mem[x10+2][15:0] = x6[15:0]».
Data Storing
Understand this scenario with real code like «sh x6, 2(x10) # mem[x10+2][15:0] = x6[15:0]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only low 16 bits of rs2 are stored
Natural alignment requires address multiple of 2
FAQ
How is the store address computed?
The effective address is the base register rs1 plus a sign-extended 12-bit byte offset.