RISC-V LD Instruction Details
Instruction ManualI-typeRV64I: load a 64-bit doubleword into rd; RV32 Zilsd: load a 64-bit value into an even/odd register pair.
Instruction Syntax
Instruction Behavior
In RV64I, LD is an I-type instruction (opcode=0000011, funct3=011) that loads a 64-bit value from rs1 plus a sign-extended 12-bit offset into rd. In the RV32 Zilsd extension, the same mnemonic/encoding means load doubleword to a register pair: the 64-bit value is written to rd and rd+1, and rd must be even. Natural alignment is an 8-byte address; under Zilsd, a 4-byte-aligned but not 8-byte-aligned access may be decomposed into two atomic word accesses and may still raise a misaligned trap.
LD Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This EEI branch applies only when the effective address is not divisible by 8; a naturally aligned access must not raise an address-misaligned exception.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This LD animation models only the RV64I single-register 64-bit load. RV32 Zilsd uses the same mnemonic and encoding but operates on an even/odd register pair; its distinct conditions are covered in the static page content.
Common Usage Scenarios
Understand this scenario with real code like «ld x10, 16(x2) # load 64-bit value from stack at offset 16».
Understand this scenario with real code like «ld x10, 16(x2) # load 64-bit value from stack at offset 16».
Pre-Use Checklist
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.