Can RV32 use LD?
RV32 requires Zilsd; this form writes an even/odd register pair rather than one RV64I register.
LD
RISC-V LD Instruction Details
Instruction ManualI-typeRV64I: load a 64-bit doubleword into rd; RV32 Zilsd: load a 64-bit value into an even/odd register pair.
Instruction Syntax
ld rd, offset(rs1)
Operand Breakdown
rd: RV64I writes one 64-bit register; RV32 Zilsd requires even rd and writes low/high 32 bits to rd/rd+1.
rs1: integer base register; offset: sign-extended 12-bit byte displacement, from -2048 through 2047.
rd=x0 discards the result; Zilsd does not write x1, while access exceptions and other side effects still apply.
RV64IZilsdMemory Load
Related Search Terms
Instruction Behavior
LD uses I-type encoding (opcode=0000011, funct3=011), addressing rs1 plus a sign-extended 12-bit byte offset. RV64I writes the 64-bit memory value to one rd. RV32 Zilsd requires even rd: low 32 bits go to rd and high 32 bits to rd+1, regardless of endianness. With rd=x0, the entire result is discarded; Zilsd does not write x1. An 8-byte-aligned access must not raise an address-misaligned exception. Zilsd does not guarantee atomicity of the whole doubleword, but each word access must be atomic when the address is divisible by 4. On a Zilsd load trap, the base register retains its original value; the other register in the pair may have been updated.
LD Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
imm
rs1
ld,()
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Assumes readable ordinary memory, with the displayed sample value at each selected effective address. Only misaligned EEI outcomes are modeled, not permissions or device side effects. Byte accesses are always naturally aligned; successful loads advance PC by 4, while exceptions stop ordinary writeback.
a0(x10)
0x0000000000001000
mem[0x0000000000001000]
0xFEDCBA9876543210
This EEI branch applies only when the effective address is not divisible by 8; a naturally aligned access must not raise an address-misaligned exception.
31..20
19..15
14..12
11..7
6..0
000000000000
imm[11:0]
01010
rs1
011
funct3
00101
rd
0000011
opcode
Execution Data Path
instruction
0x00053283
opcode
0000011 -> LOAD
funct3
011 -> LD
rd / base
t0(x5) / a0(x10)=0x0000000000001000
offset
000000000000 -> 0; ea=0x0000000000001000 (naturally aligned (8-byte))
load
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00053283
syntax : ld x5, 0(x10)
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This LD animation models only the RV64I single-register 64-bit load. RV32 Zilsd uses the same mnemonic and encoding but operates on an even/odd register pair; its distinct conditions are covered in the static page content.
Quick Understanding & Search Notes
Check XLEN first: RV64I LD writes one 64-bit register; RV32 Zilsd LD writes an even/odd register pair.
The signed 12-bit byte offset ranges from -2048 through 2047.
Odd rd encodings are reserved in Zilsd; rd=x0 discards the entire result without writing x1.
Eight-byte alignment in Zilsd prevents address-misaligned exceptions but does not guarantee whole-doubleword atomicity.
Common Usage Scenarios
RV64I or RV32 Zilsd doubleword loads
Understand this scenario with real code like «ld x10, 16(x2) # load 64-bit value from stack at offset 16».
Base plus offset addressing
Understand this scenario with real code like «ld x10, 16(x2) # load 64-bit value from stack at offset 16».
Pre-Use Checklist
Syntax Check
- Use rd, offset(rs1); offset is a signed byte displacement from -2048 through 2047.
- Select the RV64I single-register form or RV32 Zilsd even/odd register-pair form; odd rd encodings are reserved in Zilsd.
Semantic Check
- Zilsd writes low 32 bits to rd and high 32 bits to rd+1; rd=x0 discards the whole result without writing x1.
- LH/LD are naturally aligned at multiples of 2/8 respectively; the EEI determines misaligned completion or exceptions.
Pitfalls / Common Confusions
RV64I semantics load one 64-bit register; RV32 Zilsd semantics load an even/odd register pair.
Under Zilsd, rd must be even; odd rd encodings are reserved.
The offset is a sign-extended 12-bit immediate; 8-byte natural alignment is the most portable case.