RISC-V LD Instruction Details
Instruction ManualI-typeRV64I: load a 64-bit doubleword into rd; RV32 Zilsd: load a 64-bit value into an even/odd register pair.
Instruction Syntax
Instruction Encoding
LD uses opcode 0000011 (0x03), funct3 011. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Instruction Behavior
In RV64I, LD is an I-type instruction (opcode=0000011, funct3=011) that loads a 64-bit value from rs1 plus a sign-extended 12-bit offset into rd. In the RV32 Zilsd extension, the same mnemonic/encoding means load doubleword to a register pair: the 64-bit value is written to rd and rd+1, and rd must be even. Natural alignment is an 8-byte address; under Zilsd, a 4-byte-aligned but not 8-byte-aligned access may be decomposed into two atomic word accesses and may still raise a misaligned trap.
Common Usage Scenarios
Understand this scenario with real code like «ld x10, 16(x2) # load 64-bit value from stack at offset 16».
Understand this scenario with real code like «ld x10, 16(x2) # load 64-bit value from stack at offset 16».
Pre-Use Checklist
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.