What is the difference between LWU and LW in RV64I?
Both load a 32-bit word. LWU zero-extends it to 64 bits, while LW sign-extends bit 31 into the upper 32 bits.
LWU
RISC-V LWU Instruction Details
Instruction ManualI-typeLoad a 32-bit word from memory, zero-extend it to 64 bits, and write rd
Instruction Syntax
lwu rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV64IMemory Load
Instruction Behavior
LWU is an RV64I-only I-type instruction (opcode=0000011, funct3=110). It reads a 32-bit word from the effective byte address rs1 plus a sign-extended 12-bit offset, zero-extends it to 64 bits, and writes rd. A naturally aligned address is a multiple of 4; the EEI defines completion, address-misaligned exception, or access-fault behavior for a misaligned access. Unlike LW, LW sign-extends the 32-bit value to 64 bits in RV64I.
LWU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
imm
rs1
lwu,()
Execution Context
a0(x10)
0x0000000000001000
mem[0x0000000000001000]
0x80000002
This EEI branch applies only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.
31..20
19..15
14..12
11..7
6..0
000000000000
imm[11:0]
01010
rs1
110
funct3
00101
rd
0000011
opcode
Execution Data Path
instruction
0x00056283
opcode
0000011 -> LOAD
funct3
110 -> LWU
rd / base
t0(x5) / a0(x10)=0x0000000000001000
offset
000000000000 -> 0; ea=0x0000000000001000 (naturally aligned (4-byte))
load
32-bit 0x80000002 -> zero extend
x5
t0(x5) = 0x0000000080000002
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00056283
syntax : lwu t0(x5), 0(a0(x10))
result : t0(x5) = 0x0000000080000002
Architectural Result
t0(x5) = 0x0000000080000002
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
LWU is RV64I-only: it forms an effective byte address from rs1 plus a sign-extended 12-bit offset, then zero-extends the 32-bit memory value to 64 bits in rd.
In the I-type encoding, opcode=0000011 and funct3=110 identify LWU; the offset is a sign-extended 12-bit byte offset.
LWU reads 32 bits and zero-extends them to 64 bits, whereas RV64I LW sign-extends a load of the same width.
A naturally aligned 4-byte access shall not raise an address-misaligned exception; the EEI defines completion or an exception for a misaligned access.
Common Usage Scenarios
Unsigned Data Load
Understand this scenario with real code like «lwu x10, 0(x11) # load unsigned 32-bit value, x10 = zero-extend(*x11)».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
Difference from LW: LWU zero-extends, LW sign-extends
Offset range limited to ±2KB
FAQ
Can LWU execute on RV32I?
No. LWU is an RV64I-added load instruction; RV32I has no 64-bit destination register for this zero-extended result.