LWU
RISC-V LWU Instruction Details
Instruction ManualI-typeLoad 32-bit unsigned word from memory, zero-extend to 64 bits
Instruction Syntax
lwu rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV64IMemory Load
Related Search Terms
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
LWU uses opcode 0000011 (0x03), funct3 110. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0000011 (0x03)
funct3: 110 (0x6)
Instruction Behavior
LWU (I-type, opcode=0000011, funct3=110) loads a 32-bit value from memory at address rs1 + sign-extended 12-bit offset, zero-extends it to 64 bits, and writes it to rd. Unlike LW (sign-extend), LWU is for unsigned 32-bit integers. Available in RV64I only.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «lwu x10, 0(x11) # load unsigned 32-bit value, x10 = zero-extend(*x11)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Difference from LW: LWU zero-extends, LW sign-extends
Offset range limited to ±2KB