RISC-V MUL Instruction Details
Instruction ManualR-typeMultiply rs1 by rs2, store lower XLEN bits of product in rd
Instruction Syntax
Instruction Behavior
MUL performs an XLEN-bit × XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits of the product in the destination register rd. Product bits above XLEN are not written to rd. It is defined by M and is also included in Zmmul.
MUL Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Common Usage Scenarios
Understand this scenario with real code like «mul a0, a1, a2 # a0 = (a1 * a2) & ((1 << XLEN) - 1)».
Pre-Use Checklist
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.