Multiply rs1 by rs2, store lower XLEN bits of product in rd
Extension condition: RV32 or RV64 with M or Zmmul.
MUL performs an XLEN-bit × XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits of the product in the destination register rd. Product bits above XLEN are not written to rd. It is defined by M and is also included in Zmmul.
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Understand this scenario with real code like «mul a0, a1, a2 # a0 = (a1 * a2) & ((1 << XLEN) - 1)».
Yes: sources use old values and x0 discards writes. For both halves, the recommended MULH/MULHSU/MULHU then MUL pair keeps source order and a high-half destination different from both sources. This condition applies to the pair, not single-instruction legality.