MUL
RISC-V MUL Instruction Details
Instruction ManualR-typeMultiply rs1 by rs2, store lower XLEN bits of product in rd
Instruction Syntax
mul rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticMultiplication
Related Search Terms
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
MUL uses opcode 0110011 (0x33), funct3 000, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 000 (0x0)
funct7: 0000001 (0x01)
Instruction Behavior
MUL performs an XLEN-bit × XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits of the product in the destination register rd. The overflow is discarded. Part of the M standard extension.
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «mul a0, a1, a2 # a0 = (a1 * a2) & ((1 << XLEN) - 1)».
Signal Processing & DSP
Understand this scenario with real code like «mul a0, a1, a2 # a0 = (a1 * a2) & ((1 << XLEN) - 1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Overflow is truncated, only low XLEN bits kept
Use MULH for high bits of product