MULHSU
RISC-V MULHSU Instruction Details
Instruction ManualR-typeSigned×unsigned multiply, return upper XLEN bits of product
Instruction Syntax
mulhsu rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticMultiplication
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
MULHSU uses opcode 0110011 (0x33), funct3 010, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 010 (0x2)
funct7: 0000001 (0x01)
Instruction Behavior
MULHSU treats rs1 as signed and rs2 as unsigned, multiplies them, and returns the upper XLEN bits of the full product. Used in multi-word signed multiplication where the most-significant word (contains sign) multiplies with less-significant words (unsigned).
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «mulhsu t0, a0, a1 # t0 = upper XLEN bits of signed(a0) * unsigned(a1)».
Stack & Frame
Understand this scenario with real code like «mulhsu t0, a0, a1 # t0 = upper XLEN bits of signed(a0) * unsigned(a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Operand order has semantics: rs1 is signed, rs2 is unsigned, not interchangeable