RISC-V MULHSU Instruction Details
Instruction ManualR-typeSigned×unsigned multiply, return upper XLEN bits of product
Instruction Syntax
Instruction Behavior
MULHSU treats rs1 as signed and rs2 as unsigned, multiplies them, and returns the upper XLEN bits of the full product. It is used in multi-word signed multiplication where the most-significant word (which contains the sign bit) of the multiplicand multiplies less-significant, unsigned words of the multiplier. It is defined by M and is also included in Zmmul.
MULHSU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Common Usage Scenarios
Understand this scenario with real code like «mulhsu t0, a0, a1 # t0 = upper XLEN bits of signed(a0) * unsigned(a1)».
Pre-Use Checklist
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.