MULHU
RISC-V MULHU Instruction Details
Instruction ManualR-typeUnsigned multiply, return upper XLEN bits of full 2×XLEN-bit product
Instruction Syntax
mulhu rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticMultiplication
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
MULHU uses opcode 0110011 (0x33), funct3 011, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 011 (0x3)
funct7: 0000001 (0x01)
Instruction Behavior
MULHU performs unsigned×unsigned multiplication and returns the upper XLEN bits of the full 2×XLEN-bit product to rd. Combine with MUL for the full unsigned 2×XLEN-bit product (low + high).
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «mulhu t0, a0, a1 # t0 = upper XLEN bits of unsigned(a0 * a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only returns upper half
Be aware of difference from MULH (signed vs unsigned)