RISC-V MULH Instruction Details
Instruction ManualR-typeSigned multiply, return upper XLEN bits of full 2×XLEN-bit product
Instruction Syntax
Instruction Behavior
MULH performs signed×signed multiplication (both rs1 and rs2 treated as signed) and returns the upper XLEN bits of the full 2×XLEN-bit product to rd. When both halves of the same product are required, the recommended sequence is MULH followed by MUL with the same source order; the MULH destination must not equal either source. It is defined by M and is also included in Zmmul.
MULH Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Common Usage Scenarios
Understand this scenario with real code like «mulh t0, a0, a1 # t0 = upper XLEN bits of signed(a0 * a1)».
Pre-Use Checklist
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.