Signed multiply, return upper XLEN bits of full 2×XLEN-bit product
Extension condition: RV32 or RV64 with M or Zmmul.
MULH performs signed×signed multiplication (both rs1 and rs2 treated as signed) and returns the upper XLEN bits of the full 2×XLEN-bit product to rd. When both halves of the same product are required, the recommended sequence is MULH followed by MUL with the same source order; the MULH destination must not equal either source. It is defined by M and is also included in Zmmul.
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Understand this scenario with real code like «mulh t0, a0, a1 # t0 = upper XLEN bits of signed(a0 * a1)».
Yes: sources use old values and x0 discards writes. For both halves, the recommended MULH/MULHSU/MULHU then MUL pair keeps source order and a high-half destination different from both sources. This condition applies to the pair, not single-instruction legality.