MULW
RISC-V MULW Instruction Details
Instruction ManualR-typeMultiply lower 32 bits of rs1 and rs2, sign-extend lower 32-bit result to 64 bits
Instruction Syntax
mulw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticMultiplication
Related Search Terms
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
MULW uses opcode 0111011 (0x3b), funct3 000, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0111011 (0x3b)
funct3: 000 (0x0)
funct7: 0000001 (0x01)
Instruction Behavior
MULW is an RV64-only instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register. Part of the RV64M extension.
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «mulw a0, a1, a2 # a0 = sign-extend((a1[31:0] * a2[31:0])[31:0])».
Signal Processing & DSP
Understand this scenario with real code like «mulw a0, a1, a2 # a0 = sign-extend((a1[31:0] * a2[31:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only returns 32-bit product (sign-extended), upper 32 bits discarded
For full 64-bit product use MUL (if operands are properly extended)
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.