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MULW

RISC-V MULW Instruction Details

Instruction ManualR-type

Multiply lower 32 bits of rs1 and rs2, sign-extend lower 32-bit result to 64 bits

Instruction Syntax

mulw rd, rs1, rs2

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

MArithmeticMultiplication

Extension condition: RV64 only with M or Zmmul.

Related Search Terms

MULW instruction mulw syntax mulw encoding mulw sign extension mulw Zmmul mulw RV64

Instruction Behavior

MULW is an RV64-only instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register. It is defined by RV64M and is also included in RV64 Zmmul.

MULW Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1

rs2

mulw

Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

a6(x16)

0xFFFFFFFFFFFFFFF0

t2(x7)

0x0000000000000007

XLEN

31..25

24..20

19..15

14..12

11..7

6..0

0000001

funct7

00111

rs2

10000

rs1

000

funct3

00101

0111011

opcode

Execution Data Path

instruction

0x027802BB

opcode

0111011 -> OP-32

funct3

000 -> MULW

funct7

0000001 -> integer multiply selector

rd / rs1 / rs2

t0(x5) / a6(x16)=0xFFFFFFF0 (4294967280) / t2(x7)=0x00000007 (7)

32-bit multiply

Not computed

t0(x5) = 0x0000000000003001; pc = 0x0000000000002000

Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x027802BB

syntax : mulw t0(x5), a6(x16), t2(x7)

Pending result: Not computed

Current architectural state

t0(x5) = 0x0000000000003001; pc = 0x0000000000002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

rd, rs1 and rs2 are three 5-bit integer-register fields, with no immediate. A single instruction allows destination/source overlap and uses source values before writeback.

M and Zmmul use identical encodings; M implies Zmmul. MULW is RV64-only.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — M 2.0 §12.1; Zmmul 1.0 §12.3

Common Usage Scenarios

RV64 low-32-bit integer multiplication

Understand this scenario with real code like «mulw a0, a1, a2 # a0 = sign-extend((a1[31:0] * a2[31:0])[31:0])».

Pre-Use Checklist

Syntax Check

rd, rs1 and rs2 are three x0–x31 register fields (ABI aliases are accepted), with no rs3 or immediate.
M or Zmmul is required; MULW is RV64-only, while the other four operate on RV32/RV64.

Semantic Check

Multiply lower 32 bits of rs1 and rs2, sign-extend lower 32-bit result to 64 bits
Destination/source overlap uses old source values; rd=x0 discards writeback. A recommended high-half/MUL pair keeps source order and uses a high-half destination different from both sources.

Pitfalls / Common Confusions

Only the low 32 bits of each source participate; result bit 31 determines the upper 32 bits written back.

For a full 64-bit product of two 32-bit values, RV64 MUL can be used when signed sources are properly sign-extended or unsigned sources have their upper 32 bits clear.

FAQ

May rd overlap a source or be x0?

Yes: sources use old values and x0 discards writes. For both halves, the recommended MULH/MULHSU/MULHU then MUL pair keeps source order and a high-half destination different from both sources. This condition applies to the pair, not single-instruction legality.