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MULW

RISC-V MULW Instruction Details

Instruction ManualR-type

Multiply lower 32 bits of rs1 and rs2, sign-extend lower 32-bit result to 64 bits

Instruction Syntax

mulw rd, rs1, rs2

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

MArithmeticMultiplication

Related Search Terms

MULW instruction RISC-V MULW mulw syntax mulw encoding mulw R-type mulw multiply

Instruction Behavior

MULW is an RV64-only instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register. It is defined by RV64M and is also included in RV64 Zmmul.

MULW Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1

rs2

mulw

Execution Context

a6(x16)

0xFFFFFFFFFFFFFFF0

t2(x7)

0x0000000000000007

XLEN

31..12

11..7

6..0

0 0000001000 0 00000000

imm[20|10:1|11|19:12]

00101

1101111

opcode

Execution Data Path

instruction

0x010002EF

opcode

1101111 -> JAL

rd / rs1 / rs2

t0(x5) / a6(x16)=0xFFFFFFF0 (4294967280) / t2(x7)=0x00000007 (7)

32-bit multiply

4294967280 x 7 -> full[63:0]=0x00000006FFFFFF90 -> product[31:0]=0xFFFFFF90 -> sext.w 0xFFFFFFFFFFFFFF90 (low 32-bit sources; low 32-bit result is sign-extended to 64 bits)

t0(x5) = 0xFFFFFFFFFFFFFF90

Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x010002EF

syntax : mulw t0(x5), a6(x16), t2(x7)

result : t0(x5) = 0xFFFFFFFFFFFFFF90

Architectural Result

t0(x5) = 0xFFFFFFFFFFFFFF90

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Common Usage Scenarios

RV64 low-32-bit integer multiplication

Understand this scenario with real code like «mulw a0, a1, a2 # a0 = sign-extend((a1[31:0] * a2[31:0])[31:0])».

Pre-Use Checklist

Syntax Check

Verify rd, rs1, rs2 (and rs3) are valid GPRs.
Confirm funct3 and funct7 encoding is correct.

Semantic Check

Check if the result affects subsequent branches or address calculations.
Ensure the rd register is not overwritten by another instruction.

Pitfalls / Common Confusions

Only returns 32-bit product (sign-extended), upper 32 bits discarded

For full 64-bit product use MUL (if operands are properly extended)

W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.

These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.