RISC-V DIVW Instruction Details
Instruction ManualR-typeDivide lower 32 bits of rs1 by lower 32 bits of rs2 (signed), sign-extend 32-bit quotient to 64 bits
Instruction Syntax
Instruction Behavior
DIVW is an RV64-only signed division instruction that divides the lower 32 bits of rs1 by the lower 32 bits of rs2 (both signed), rounds toward zero, and sign-extends the 32-bit quotient to 64 bits. Division by zero and overflow behavior mirrors DIV (at 32-bit width).
DIVW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Common Usage Scenarios
Understand this scenario with real code like «divw a0, a1, a2 # a0 = sign-extend(signed(a1[31:0]) / signed(a2[31:0]))».
Pre-Use Checklist
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.