Does REMW use the complete 64-bit source operands?
No. REMW uses only the low 32 bits of rs1 and rs2 as signed operands, then sign-extends the final 32-bit remainder to 64 bits.
REMW
RISC-V REMW Instruction Details
Instruction ManualR-typeSigned remainder of 32-bit division, sign-extended to 64 bits
Instruction Syntax
remw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Behavior
REMW is an RV64-only signed remainder instruction. The lower 32 bits of rs1 divided by rs2 (both signed), remainder sign-extended to 64 bits. Sign of nonzero result equals sign of dividend. Division by zero: remainder = dividend. Overflow: remainder = 0.
REMW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
remw
,
,
Execution Context
t1(x6)
0x0000000000000014
t2(x7)
0x0000000000000007
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
110
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x027362BB
opcode
0111011 -> OP-32
funct3
110 -> REMW
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
signed 32-bit remainder
20 % 7 -> remainder[31:0]=0x00000006 -> sext.w 0x0000000000000006 (signed 32-bit remainder; a nonzero result has the dividend sign)
x5
t0(x5) = 0x0000000000000006
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027362BB
syntax : remw t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x0000000000000006
Architectural Result
t0(x5) = 0x0000000000000006
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
REMW is RV64-only: it takes a signed remainder from the low 32 bits of both sources, then sign-extends that 32-bit result to 64 bits in rd.
The fixed OP-32 R-type encoding is opcode=0111011, funct3=110, and funct7=0000001; REMW is an RV64M instruction.
With a zero divisor, the low 32-bit remainder equals the low 32-bit dividend and is still sign-extended; most-negative 32-bit divided by -1 returns zero.
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «remw a0, a1, a2 # a0 = sign-extend(signed(a1[31:0]) % signed(a2[31:0]))».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Division by zero returns dividend (sign-extended to 64 bits)
Remainder sign follows dividend
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.