Why is an unsigned REMUW remainder still sign-extended?
Unsignedness determines how the low 32-bit remainder is calculated; as a W instruction, REMUW then sign-extends that 32-bit result to 64 bits.
REMUW
RISC-V REMUW Instruction Details
Instruction ManualR-typeUnsigned remainder of 32-bit division, sign-extended to 64 bits
Instruction Syntax
remuw rd, rs1, rs2
Operand Breakdown
rd: receives the result; source/destination overlap uses old source values, and rd=x0 discards writeback.
rs1 is the dividend and rs2 the divisor; compute the remainder using unsigned low 32-bit values.
Requires RV64 M; always sign-extend the 32-bit remainder to 64 bits, including with a zero divisor.
MArithmeticDivision
Instruction Behavior
REMUW is an RV64 M-extension unsigned remainder instruction. It uses the low 32 bits of both rs1 and rs2 and always sign-extends the 32-bit remainder to 64 bits. A zero divisor returns the low 32-bit dividend, sign-extended to 64 bits. Unsigned division cannot overflow.
REMUW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
remuw
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x0000000000000014
t2(x7)
0x0000000000000007
This selector chooses specification-defined division-result branches. Division presets set the displayed t1/t2 initial values; editing a source register restores normal mode. It is not a trap or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
111
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x027372BB
opcode
0111011 -> OP-32
funct3
111 -> REMUW
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
unsigned 32-bit remainder
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027372BB
syntax : remuw t0(x5), t1(x6), t2(x7)
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
REMUW is RV64-only: it takes an unsigned remainder from the low 32 bits of both sources, then sign-extends that 32-bit value from bit 31 to 64 bits in rd.
The fixed OP-32 R-type encoding is opcode=0111011, funct3=111, and funct7=0000001; REMUW is an RV64M instruction.
With a zero divisor, the low 32-bit remainder equals the low 32-bit dividend and is still sign-extended; unsigned division cannot overflow.
Common Usage Scenarios
Integer remainder
RV64 plus M, x6=20 and x7=7: remuw x5, x6, x7 gives x5=6; the low 32-bit sources are unsigned, but the remainder is still sign-extended to 64 bits.
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 select x0–x31 or ABI aliases, with no immediate or rs3.
Semantic Check
- REMUW is RV64-only: it takes an unsigned remainder from the low 32 bits of both sources, then sign-extends that 32-bit value from bit 31 to 64 bits in rd.
- Destination/source overlap uses old source values; x0 is always zero and writes to it are discarded.
Pitfalls / Common Confusions
A zero divisor raises no integer divide-by-zero arithmetic exception; the remainder equals the low 32-bit dividend, sign-extended to 64 bits.
Unsigned division cannot overflow.
Requires RV64 M: use only the low 32-bit sources and always sign-extend the result to 64 bits; unavailable on RV32.