Why is an unsigned REMUW remainder still sign-extended?
Unsignedness determines how the low 32-bit remainder is calculated; as a W instruction, REMUW then sign-extends that 32-bit result to 64 bits.
REMUW
RISC-V REMUW Instruction Details
Instruction ManualR-typeUnsigned remainder of 32-bit division, sign-extended to 64 bits
Instruction Syntax
remuw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Instruction Behavior
REMUW is an RV64-only unsigned remainder instruction. The lower 32 bits of rs1 divided by rs2 (both unsigned), remainder sign-extended to 64 bits. Division by zero: remainder = dividend (sign-extended). Unsigned division cannot overflow.
REMUW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
remuw
,
,
Execution Context
t1(x6)
0x0000000000000014
t2(x7)
0x0000000000000007
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
111
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x027372BB
opcode
0111011 -> OP-32
funct3
111 -> REMUW
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
unsigned 32-bit remainder
20 % 7 -> remainder[31:0]=0x00000006 -> sext.w 0x0000000000000006 (unsigned 32-bit remainder)
x5
t0(x5) = 0x0000000000000006
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027372BB
syntax : remuw t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x0000000000000006
Architectural Result
t0(x5) = 0x0000000000000006
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
REMUW is RV64-only: it takes an unsigned remainder from the low 32 bits of both sources, then sign-extends that 32-bit value from bit 31 to 64 bits in rd.
The fixed OP-32 R-type encoding is opcode=0111011, funct3=111, and funct7=0000001; REMUW is an RV64M instruction.
With a zero divisor, the low 32-bit remainder equals the low 32-bit dividend and is still sign-extended; unsigned division cannot overflow.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «remuw a0, a1, a2 # a0 = sign-extend(unsigned(a1[31:0]) % unsigned(a2[31:0]))».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Division by zero returns dividend (sign-extended to 64 bits)
Unsigned overflow cannot occur
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.