What is the core difference between REMU and REM?
REMU interprets both source registers as unsigned XLEN-bit integers. REM interprets them as signed integers, with a nonzero remainder following the dividend sign.
REMU
RISC-V REMU Instruction Details
Instruction ManualR-typeUnsigned remainder of rs1 / rs2, stored in rd
Instruction Syntax
remu rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Behavior
REMU provides the remainder of unsigned division of rs1 by rs2. On division by zero, the remainder equals the dividend. Unsigned division cannot overflow.
REMU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
remu
,
,
Execution Context
t1(x6)
0x00000014
t2(x7)
0x00000007
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
111
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x027372B3
opcode
0110011 -> OP
funct3
111 -> REMU
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
unsigned 32-bit remainder
20 % 7 -> remainder[31:0]=0x00000006 (unsigned 32-bit remainder)
x5
t0(x5) = 0x00000006
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027372B3
syntax : remu t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000006
Architectural Result
t0(x5) = 0x00000006
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
REMU treats both rs1 and rs2 as XLEN-bit unsigned values, computes their remainder, and writes rd. Its unsigned interpretation differs from REM; the mnemonic change is semantic.
The fixed R-type encoding is opcode=0110011, funct3=111, and funct7=0000001; REMU belongs to the M extension.
A zero divisor returns the dividend as the remainder; unsigned division has no signed most-negative divided-by--1 overflow case.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «remu a0, a1, a2 # a0 = a1 % a2 (unsigned)».
Type Conversion
Understand this scenario with real code like «remu a0, a1, a2 # a0 = a1 % a2 (unsigned)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Division by zero returns dividend, no trap