What is the core difference between REMU and REM?
REMU interprets both source registers as unsigned XLEN-bit integers. REM interprets them as signed integers, with a nonzero remainder following the dividend sign.
REMU
RISC-V REMU Instruction Details
Instruction ManualR-typeUnsigned remainder of rs1 / rs2, stored in rd
Instruction Syntax
remu rd, rs1, rs2
Operand Breakdown
rd: receives the result; source/destination overlap uses old source values, and rd=x0 discards writeback.
rs1 is the dividend and rs2 the divisor; compute the remainder using unsigned XLEN-bit values.
Requires RV32/RV64 M; a zero divisor returns the dividend without an integer divide-by-zero arithmetic exception.
MArithmeticDivision
Related Search Terms
Instruction Behavior
REMU provides the XLEN-bit unsigned remainder of rs1 divided by rs2. A zero divisor returns the dividend. Unsigned division cannot overflow.
REMU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
remu
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x00000014
t2(x7)
0x00000007
This selector chooses specification-defined division-result branches. Division presets set the displayed t1/t2 initial values; editing a source register restores normal mode. It is not a trap or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
111
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x027372B3
opcode
0110011 -> OP
funct3
111 -> REMU
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
unsigned 32-bit remainder
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027372B3
syntax : remu t0(x5), t1(x6), t2(x7)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
REMU treats both rs1 and rs2 as XLEN-bit unsigned values, computes their remainder, and writes rd. Its unsigned interpretation differs from REM; the mnemonic change is semantic.
The fixed R-type encoding is opcode=0110011, funct3=111, and funct7=0000001; REMU belongs to the M extension.
A zero divisor returns the dividend as the remainder; unsigned division has no signed most-negative divided-by--1 overflow case.
Common Usage Scenarios
Integer remainder
RV32/RV64 plus M, x6=20 and x7=7: remu x5, x6, x7 gives x5=6, interpreting both sources as XLEN-bit unsigned integers.
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 select x0–x31 or ABI aliases, with no immediate or rs3.
Semantic Check
- REMU treats both rs1 and rs2 as XLEN-bit unsigned values, computes their remainder, and writes rd. Its unsigned interpretation differs from REM; the mnemonic change is semantic.
- Destination/source overlap uses old source values; x0 is always zero and writes to it are discarded.
Pitfalls / Common Confusions
A zero divisor raises no integer divide-by-zero arithmetic exception; the remainder equals the dividend.
Unsigned division cannot overflow.