DIVU
RISC-V DIVU Instruction Details
Instruction ManualR-typeUnsigned division: rs1 / rs2, quotient stored in rd
Instruction Syntax
divu rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
DIVU uses opcode 0110011 (0x33), funct3 101, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 101 (0x5)
funct7: 0000001 (0x01)
Instruction Behavior
DIVU performs unsigned integer division of rs1 by rs2. On division by zero, the quotient has all bits set (2^XLEN-1, the largest unsigned number). Unsigned division cannot overflow.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «divu a0, a1, a2 # a0 = unsigned(a1 / a2)».
Multiplication & Division
Understand this scenario with real code like «divu a0, a1, a2 # a0 = unsigned(a1 / a2)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Division by zero returns all-1s (max unsigned), no trap
Unsigned overflow cannot occur