Does DIVU division by zero trap?
No. The specification defines an all-ones quotient; the instruction itself does not raise an integer divide-by-zero exception.
DIVU
RISC-V DIVU Instruction Details
Instruction ManualR-typeUnsigned division: rs1 / rs2, quotient stored in rd
Instruction Syntax
divu rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Behavior
DIVU performs unsigned integer division of rs1 by rs2. On division by zero, the quotient has all bits set (2^XLEN-1, the largest unsigned number). Unsigned division cannot overflow.
DIVU Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
divu
,
,
Execution Context
t1(x6)
0x00000014
t2(x7)
0x00000007
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
101
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x027352B3
opcode
0110011 -> OP
funct3
101 -> DIVU
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
unsigned 32-bit division
20 / 7 -> quotient[31:0]=0x00000002 (unsigned 32-bit division)
x5
t0(x5) = 0x00000002
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027352B3
syntax : divu t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000002
Architectural Result
t0(x5) = 0x00000002
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
DIVU uses an M-extension R-type encoding to divide rs1 by rs2 as XLEN-bit unsigned integers. A zero divisor produces an all-ones quotient; this is not an exception path, and unsigned division has no overflow special case.
funct7=0000001, funct3=101, and the OP opcode select DIVU.
DIVU interprets both sources as XLEN-bit unsigned integers; a zero divisor produces 2^XLEN-1.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «divu a0, a1, a2 # a0 = unsigned(a1 / a2)».
Multiplication & Division
Understand this scenario with real code like «divu a0, a1, a2 # a0 = unsigned(a1 / a2)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Division by zero returns all-1s (max unsigned), no trap
Unsigned overflow cannot occur