What does DIV write for integer division by zero?
It writes all ones to rd, which is -1 under signed interpretation.
DIV
RISC-V DIV Instruction Details
Instruction ManualR-typeSigned division: rs1 / rs2, quotient stored in rd (round toward zero)
Instruction Syntax
div rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Behavior
DIV is M-extension XLEN-bit signed integer division: rs1 is the dividend, rs2 is the divisor, and the quotient is rounded toward zero and written to rd. With a zero divisor the quotient is all ones (-1); signed overflow occurs only for the most-negative integer divided by -1, where the quotient equals the dividend.
DIV Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
div
,
,
Execution Context
t1(x6)
0x00000014
t2(x7)
0x00000007
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x027342B3
opcode
0110011 -> OP
funct3
100 -> DIV
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
signed 32-bit division
20 / 7 -> quotient[31:0]=0x00000002 (signed 32-bit division rounds toward zero)
x5
t0(x5) = 0x00000002
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027342B3
syntax : div t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000002
Architectural Result
t0(x5) = 0x00000002
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
DIV uses the M-extension R-type encoding for signed XLEN division rounded toward zero; both division by zero and most-negative divided by -1 have specification-defined quotients.
DIV is selected by funct7=0000001, funct3=100, and the OP opcode in the M extension.
A zero divisor produces an all-ones quotient; only most-negative divided by -1 overflows signed division, and its quotient equals the dividend.
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «div a0, a1, a2 # a0 = signed(a1 / a2), toward zero».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Division by zero returns all bits set (-1); DIV defines a result rather than an arithmetic exception
Overflow: most-negative / -1 returns dividend, remainder=0
FAQ
Does DIV round toward negative infinity?
No. The specification defines signed DIV quotient rounding toward zero.