Does REM raise an arithmetic exception on division by zero?
No. The M extension specifies that REM writes the dividend to rd as the remainder when the divisor is zero.
REM
RISC-V REM Instruction Details
Instruction ManualR-typeSigned remainder of rs1 / rs2, stored in rd
Instruction Syntax
rem rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Behavior
REM provides the XLEN-bit signed remainder of rs1 divided by rs2. A nonzero remainder has the dividend sign; a zero divisor returns the dividend; only most-negative divided by -1 overflows and returns zero. Except for overflow, dividend = divisor x quotient + remainder.
REM Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
rem
,
,
Execution Context
t1(x6)
0x00000014
t2(x7)
0x00000007
This selector chooses only specification-defined division-result branches; it is not an exception, trap, or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
110
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x027362B3
opcode
0110011 -> OP
funct3
110 -> REM
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
signed 32-bit remainder
20 % 7 -> remainder[31:0]=0x00000006 (signed 32-bit remainder; a nonzero result has the dividend sign)
x5
t0(x5) = 0x00000006
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027362B3
syntax : rem t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x00000006
Architectural Result
t0(x5) = 0x00000006
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
REM is the M-extension signed XLEN-bit remainder operation: rs1 is the dividend and rs2 is the divisor; the normal remainder is written to rd, and a nonzero remainder has the dividend sign.
The fixed R-type encoding is opcode=0110011, funct3=110, and funct7=0000001; REM belongs to the M extension.
A zero divisor returns the dividend as the remainder; signed overflow occurs only for most-negative divided by -1, where the remainder is zero.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «rem a0, a1, a2 # a0 = a1 % a2 (signed)».
Multiplication & Division
Understand this scenario with real code like «rem a0, a1, a2 # a0 = a1 % a2 (signed)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Division by zero returns dividend, no trap
Remainder sign follows dividend, not divisor
The dividend identity excludes the signed-overflow case