REM
RISC-V REM Instruction Details
Instruction ManualR-typeSigned remainder of rs1 / rs2, stored in rd
Instruction Syntax
rem rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
REM uses opcode 0110011 (0x33), funct3 110, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 110 (0x6)
funct7: 0000001 (0x01)
Instruction Behavior
REM provides the remainder of signed division of rs1 by rs2. The sign of a nonzero result equals the sign of the dividend. On division by zero, remainder equals the dividend. On overflow, remainder is zero. The identity dividend = divisor × quotient + remainder holds.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «rem a0, a1, a2 # a0 = a1 % a2 (signed)».
Multiplication & Division
Understand this scenario with real code like «rem a0, a1, a2 # a0 = a1 % a2 (signed)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Division by zero returns dividend, no trap
Remainder sign follows dividend, not divisor
Identity: dividend = divisor × quotient + remainder