DIVUW
RISC-V DIVUW Instruction Details
Instruction ManualR-typeDivide lower 32 bits of rs1 by lower 32 bits of rs2 (unsigned), sign-extend 32-bit quotient to 64 bits
Instruction Syntax
divuw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Related Search Terms
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
DIVUW uses opcode 0111011 (0x3b), funct3 101, funct7 0000001. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0111011 (0x3b)
funct3: 101 (0x5)
funct7: 0000001 (0x01)
Instruction Behavior
DIVUW is an RV64-only unsigned division instruction that divides the lower 32 bits of rs1 by the lower 32 bits of rs2 (both unsigned), sign-extends the 32-bit quotient to 64 bits. Division by zero returns all-1s (2^32-1 sign-extended to 64 bits = -1).
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «divuw a0, a1, a2 # a0 = sign-extend(unsigned(a1[31:0]) / unsigned(a2[31:0]))».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Division by zero returns all-1s (sign-extended to -1 in 64-bit), no trap
Unsigned overflow cannot occur
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.