How does DIVUW handle the upper 32 bits?
Source upper halves are ignored; quotient bit 31 is sign-extended through the destination upper half.
DIVUW
RISC-V DIVUW Instruction Details
Instruction ManualR-typeDivide lower 32 bits of rs1 by lower 32 bits of rs2 (unsigned), sign-extend 32-bit quotient to 64 bits
Instruction Syntax
divuw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
MArithmeticDivision
Instruction Behavior
DIVUW is an RV64-only unsigned division instruction that divides the lower 32 bits of rs1 by the lower 32 bits of rs2 (both unsigned), sign-extends the 32-bit quotient to 64 bits. Division by zero returns all-1s (2^32-1 sign-extended to 64 bits = -1).
DIVUW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
divuw
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x0000000000000014
t2(x7)
0x0000000000000007
This selector chooses specification-defined division-result branches. Division presets set the displayed t1/t2 initial values; editing a source register restores normal mode. It is not a trap or performance model.
31..25
24..20
19..15
14..12
11..7
6..0
0000001
funct7
00111
rs2
00110
rs1
101
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x027352BB
opcode
0111011 -> OP-32
funct3
101 -> DIVUW
funct7
0000001 -> M-extension divide/remainder selector
rd / dividend / divisor
t0(x5) / t1(x6)=20 / t2(x7)=7
unsigned 32-bit division
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x027352BB
syntax : divuw t0(x5), t1(x6), t2(x7)
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
DIVUW divides the low 32 bits of both sources as unsigned integers, then sign-extends the 32-bit quotient to 64 bits. Source upper halves do not participate.
RV64 M R-type encoding: funct7=0000001, funct3=101, opcode=0111011 (OP-32).
A zero low-32-bit divisor writes 0xffffffffffffffff without an integer divide-by-zero exception.
Unsigned division cannot overflow; the quotient is still sign-extended, not zero-extended.
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «divuw x10, x11, x12 # quotient uses unsigned low 32-bit sources; sign-extend to 64 bits».
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 are three x0–x31 register fields (ABI aliases are accepted), with no rs3 or immediate.
Semantic Check
- Use only low 32-bit sources and sign-extend the 32-bit quotient to 64 bits; RV64 M is required.
- rd=x0 discards writeback; overlapping sources and destinations use old source values. Divide by zero and signed overflow raise no integer arithmetic exception.
Pitfalls / Common Confusions
Division by zero returns all-1s (sign-extended to -1 in 64-bit), no trap
Unsigned overflow cannot occur
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
DIVUW requires RV64 and M; it is absent from RV32 and from the multiplication-only Zmmul extension.