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CSR Bit Fields

RISC-V hpmcounter18 CSR Register

Address 0xC12Privilege UserAccess RO / 64 bits (RV32 accesses the upper 32 bits through hpmcounter18h)User counters and performance-monitoring CSRs

hpmcounter18 is a Zihpm user-level read-only hardware performance counter; its event, implemented count, and width are platform-specific.

Related Search Terms
hpmcounter18 CSRhpmcounter18 0xC12HPM counter 18hardware performance counter 18mcounteren HPM18mhpmevent18
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand hpmcounter18 By Bit Fields

1 key fields
63:0

VALUE

RO

hpmcounter18 reads the complete 64-bit count on RV64; the implemented count, width, and events are platform-specific.

VALUE (bits 63:0) — hpmcounter18 reads the complete 64-bit count on RV64; the implemented count, width, and events are platform-specific.

What This Field Controls

  • - hpmcounter18 reads the complete 64-bit count on RV64; the implemented count, width, and events are platform-specific.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hpmcounter18 is the Zihpm user read-only counter at 0xC12. Its event, implemented count, and width are platform-specific; hpmcounter18h provides the RV32 upper 32 bits.

hpmcounter18 is URO at 0xC12 in the official CSR table and is a read-only shadow of mhpmcounter18.
Zihpm depends on Zicsr and supplies up to 29 performance counters, while the platform determines whether this counter is implemented, its width, and its event.
In S/U mode, a clear mcounteren.HPM18 causes an illegal-instruction exception on read; when scounteren is implemented, its HPM18 bit controls U-mode access.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - Confirm that Zihpm (which depends on Zicsr) and this counter are implemented. Accessing an unimplemented counter may raise an illegal-instruction exception or return a constant value.
  • - In S/U mode, reading raises an illegal-instruction exception when mcounteren.HPM18 is clear; when scounteren is implemented, its HPM18 bit also controls U-mode access.
  • - A misconfigured event-selection configuration may cause the counter to return a constant value.

Risk Checks Before Writing

  • - hpmcounter18 is a read-only shadow of mhpmcounter18; do not write this user-level CSR.

Put It Back Into A Real Flow

1

Use the execution environment interface to confirm the implemented count, width, and event configuration.

2

Check the mcounteren/scounteren permission required at the current privilege level.

3

Read hpmcounter18; RV32 also needs hpmcounter18h to obtain the full 64-bit value.

FAQ

Is hpmcounter18 always readable?

No. An unimplemented counter may raise an illegal-instruction exception or return a constant value; S/U-mode access also requires mcounteren.HPM18, and U-mode access requires scounteren.HPM18 when scounteren is implemented.

How does RV32 read the full hpmcounter18?

This CSR reads the low 32 bits; hpmcounter18h reads the upper 32 bits of the same 64-bit counter.