RISC-V hpmcounter21 CSR Register

Address 0xC15Privilege UserAccess RO / XLENUser counters and performance-monitoring CSRs

hpmcounter21 is a user-level hardware performance-monitoring counter CSR for implementation-defined event counts.

Related Search Terms

hpmcounter21 CSR hpmcounter21 0xC15 HPM counter 21 hardware performance counter 21 mcounteren HPM21 mhpmevent21

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0RO

Field Map

Understand hpmcounter21 By Bit Fields

1 key fields

XLEN-1:0

VALUE

Full register value of hpmcounter21; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

VALUE (bits XLEN-1:0) — Full register value of hpmcounter21; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

What This Field Controls

- Full register value of hpmcounter21; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

hpmcounter21 is a RO CSR in user counters and performance-monitoring csrs at 0xC15. Check privilege and implemented extensions before interpreting its bit fields.

hpmcounter21 address, lowest access privilege, and access class are checked against the official CSR table: 0xC15, User, RO.

hpmcounter21 belongs to the unprivileged counter/timer path; lower-privilege access can also depend on counteren-style CSRs.

This is a read-only CSR; do not write it. Ignore reserved or WPRI field values on reads, and preserve unchanged fields when writing writable CSRs.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements hpmcounter21; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0xC15 and the lowest access privilege (User) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- hpmcounter21 is a read-only CSR; writes raise an illegal-instruction exception or are disallowed by the implementation.

Put It Back Into A Real Flow

Read hpmcounter21 to obtain hardware or runtime state.

Interpret the returned value according to the field descriptions and do not attempt to write it back.

If reading fails at the current privilege level, handle the illegal-instruction exception path.

FAQ

Can hpmcounter21 be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records hpmcounter21 as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when using hpmcounter21?

hpmcounter21 is read-only. Treat it as an observation point, do not try to write it, and do not depend on fixed values for reserved or WPRI fields.